Patent US6683930B1 successfully refreshed from Google Patents.
US6683930B1
Expired / Lapsed
US
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Digital phase/frequency detector, and clock generator and data recovery PLL containing the same
Assignee: RPX Corp
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Filing: 1999-12-23
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Granted: 2004-01-27
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Expires: 2019-12-23
Abstract
Abstract An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate in response to an input signal having a second data rate and clock signal having the second data rate. The second circuit may be configured to generate a second output signal in response to the input signal and the clock signal. The logic circuit may be configured to generate a clock signal in response to the first output signal and the second output signal.
Inventors
- 👤 Kamal Dalmia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:53
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
95 words
An apparatus comprising: a phase detector circuit configured to generate a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate; a frequency detector circuit configured to generate a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal.
Claim 2
Independent Claim
95 words
An apparatus comprising: a phase detector circuit configured to generate a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate; a frequency detector circuit configured to generate a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal.
Claim 3
Dependent Claim
27 words
The apparatus according to claim 1 , wherein said phase detector circuit is further configured to generate a first recovered data signal having said second data rate.
Claim 4
Dependent Claim
27 words
The apparatus according to claim 1 , wherein said phase detector circuit comprises a digital linear phase detector and said frequency circuit comprises a digital frequency detector.
Claim 5
Dependent Claim
17 words
The apparatus according to claim 2 , wherein said first data signal comprises a re-timed data signal.
Claim 6
Dependent Claim
16 words
The apparatus according to claim 1 , wherein said clock signal comprises a recovered clock signal.
Claim 7
Dependent Claim
31 words
The apparatus according to claim 1 , wherein said first data rate, said second data rate and said third data rate are the same data rate or a different data rate.
Claim 8
Dependent Claim
33 words
The apparatus according to claim 1 , wherein said first and said second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.
Claim 9
Dependent Claim
26 words
The apparatus according to claim 5 , wherein (i) said first output signal and/or (ii) said second output signal is configured to control said logic circuit.
Claim 10
Dependent Claim
38 words
The apparatus according to claim 7 , wherein said logic circuit comprises (i) a gate, (ii) a charge pump and filter circuit and (iii) a VCO, wherein said gate is configured to receive said first and second signals.
Claim 11
Dependent Claim
36 words
The apparatus according to claim 9 , wherein said charge pump and said filter circuit are configured to control said VCO in response to said gate, wherein said VCO is configured to generate said clock signal.
Claim 12
Dependent Claim
28 words
The apparatus according to claim 9 , wherein said gate (i) comprises a digital OR gate and (ii) is configured to digitally combine said first and second signals.
Claim 13
Dependent Claim
19 words
The apparatus according to claim 11 , wherein said apparatus comprises a reference-less dual loop clock and data architecture.
Claim 14
Independent Claim
94 words
An apparatus comprising: means for using a phase detector for generating a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate; means for using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and means for generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
Claim 15
Independent Claim
94 words
An apparatus comprising: means for using a phase detector for generating a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate; means for using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and means for generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
Claim 16
Independent Claim
97 words
A method for clock data recovery comprising the steps of: (A) using a phase detector for generating a first output signal having a first data rate in response to (i) data input signal having a second data rate and (ii) a clock signal having said second data rate; (B) using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and (C) generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
Claim 17
Independent Claim
97 words
A method for clock data recovery comprising the steps of: (A) using a phase detector for generating a first output signal having a first data rate in response to (i) data input signal having a second data rate and (ii) a clock signal having said second data rate; (B) using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal; and (C) generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
Claim 18
Dependent Claim
26 words
The method according to claim 14 , wherein step (A) further comprises the sub-step of: (A-1) generating a first data signal having said second data rate.
Claim 19
Dependent Claim
17 words
The method according to claim 15 , wherein said first data signal comprises a re-timed data signal.
Claim 20
Dependent Claim
16 words
The method according to claim 14 , wherein said clock signal comprises a recovered clock signal.
Claim 21
Dependent Claim
32 words
The method according to claim 14 , wherein said first and second output signals are (i) both pump-up signals, (ii) both pump-down signals or (iii) a combination of pump-up and pump-down signals.
Claim 22
Dependent Claim
23 words
The method according to claim 14 , wherein (i) said first and/or (ii) said second signal controls the generation of said clock signal.
Claim 23
Dependent Claim
20 words
The method according to claim 14 , wherein said step (C) further comprises adding said first and second output signals.
Claim 24
Dependent Claim
19 words
The apparatus according to claim 1 , wherein said apparatus comprises a reference-less dual loop clock and data architecture.
References Cited (Backward Citations)
US4594564A
Cited
US4593254A
Cited
US4940952A
Cited
US4943788A
Cited
US4926447A
Cited
US5550878A
Cited
US5506875A
Cited
US5574756A
Cited
US5838749A
Cited
US5719908A
Cited
US6041090A
Cited
US5739709A
Cited
US5712580A
Cited
US5799048A
Cited
US5953386A
Cited
US5694088A
Cited
US6055286A
Cited
US6215835B1
Cited
US5950115A
Cited
US5910753A
Cited
US6347128B1
Cited
US6081572A
Cited
US6075416A
Cited
US6535527B1
Cited
US6351508B1
Cited
US6307413B1
Cited
US6310521B1
Cited
US6366135B1
Cited
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