US6347128B1
Expired / Lapsed
US
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Self-aligned clock recovery circuit with proportional phase detector
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-07-20
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Granted: 2002-02-12
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Expires: 2018-07-20
Abstract
Abstract A self-aligned clock recovery circuit for synchronizing a local clock with an input data signal includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector obtains samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and obtains a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples. Logic circuitry determines whether the local clock appears to be early or late based on a comparison of the logic levels of the symbol samples and the associated data crossover sample, and provides a corresponding output signal through a filter to the local clock to adjust the clock accordingly. Since the relative sampling instants of successive data crossover samples are varied with time, the phase detector output signal amplitude is substantially proportional to the amount of phase error between the local clock and the symbol timing, thereby improving jitter properties of the clock recovery circuit.
Inventors
- 👤 Johannes Gerardus Ransijn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:22
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03D; H03D13/00; H03D13/003; H03D13/004; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/085; H03L7/091
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
204 words
A clock recovery circuit for synchronizing a local clock of a local clock generator with symbol timing of an input data signal, comprising: means for phase shifting said local clock by a time varying phase shift to provide a phase shifted clock signal, wherein said time varying phase shift is characterized by a piecewise continuous symmetrical function; sampling circuitry for obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to pulses of said local clock, and for obtaining a third sample of said data signal, responsive to a transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, said third sampling instant varying in time for each symbol sample relative to said first and second sampling instants; logic circuitry operative to determine, based on said first, second and third data samples, whether the clock appears to be early or late and to provide an output signal in accordance with the determination; and a filter, for filtering said output signal and providing the filtered signal to said local clock generator to adjust the local clock accordingly and thereby synchronize the local clock to the symbol timing.
Claim 2
Dependent Claim
204 words
A clock recovery circuit for synchronizing a local clock of a local clock generator with symbol timing of an input data signal, comprising: means for phase shifting said local clock by a time varying phase shift to provide a phase shifted clock signal, wherein said time varying phase shift is characterized by a piecewise continuous symmetrical function; sampling circuitry for obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to pulses of said local clock, and for obtaining a third sample of said data signal, responsive to a transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, said third sampling instant varying in time for each symbol sample relative to said first and second sampling instants; logic circuitry operative to determine, based on said first, second and third data samples, whether the clock appears to be early or late and to provide an output signal in accordance with the determination; and a filter, for filtering said output signal and providing the filtered signal to said local clock generator to adjust the local clock accordingly and thereby synchronize the local clock to the symbol timing.
Claim 3
Dependent Claim
45 words
The clock recovery circuit of claim 1 wherein said time varying phase shift is sufficient to enable said output signal to be provided with a mean amplitude substantially proportional to the phase error between the local clock and the symbol timing of the data signal.
Claim 4
Dependent Claim
45 words
The clock recovery circuit of claim 1 wherein said time varying phase shift is a phase shift selected from the group consisting of a sinusoidally varying phase shift, a phase shift varying as a sawtooth waveform, and a phase shift varying as a triangular wave.
Claim 5
Dependent Claim
41 words
The clock recovery circuit of claim 1 wherein said first and second data samples are samples of consecutive symbols of said data signal and said first and second sampling instants correspond to edge transitions of consecutive pulses of said local clock.
Claim 6
Dependent Claim
15 words
The clock recovery circuit of claim 1 wherein said data signal is a bit stream.
Claim 7
Dependent Claim
157 words
The clock recovery circuit of claim 1 wherein said sampling circuitry comprises: a first sampling circuit for sampling said input data signal; a second sampling circuit for receiving a data output of said first sampling circuit, said first and second sampling circuits being clocked in synchronism by said local clock such that at a given time, said first and second sampling circuits output said first and second data samples, respectively; third and fourth sampling circuits, said third sampling circuit having a data input for receiving said input data signal and providing a data output to said fourth sampling circuit, said fourth sampling circuit being clocked by said local clock, said third sampling circuit being clocked by said phase shifted clock signal so that an output of said fourth sampling circuit at said given time represents said data crossover sample which is taken at a variable data crossover sampling instant relative to said first and second sampling instants.
Claim 8
Dependent Claim
17 words
The clock recovery circuit of claim 6 wherein each of said sampling circuits include a D flip-flop.
Claim 9
Dependent Claim
84 words
The clock recovery circuit of claim 6 wherein said logic circuitry comprises first and second exclusive OR gates and a subtracter, with said data outputs of said first and fourth sampling circuits being inputted to said first exclusive OR gate, said data outputs of said second and fourth sampling circuits being inputted to said second exclusive OR gate, and said subtracter subtracting the output of said first exclusive OR gate from the output of said second exclusive OR gate to provide said output signal.
Claim 10
Dependent Claim
17 words
The clock recovery circuit of claim 1 wherein said local clock generator is a voltage controlled oscillator.
Claim 11
Dependent Claim
21 words
The clock recovery circuit of claim 1 , further comprising a frequency detector coupled between said logic circuitry and said filter.
Claim 12
Independent Claim
176 words
A method of synchronizing a local clock with symbol timing of an input data signal, comprising the steps of: obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to edge transitions of said local clock; phase shifting said clock by a piecewise continuous symmetrical time varying phase shifting function to provide a phase shifted clock signal and obtaining a third data sample of said data signal, responsive to an edge transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, wherein said third sampling instant varies for each symbol sample relative to said first and second sampling instants; determining, based on said first, second and third data samples, whether the clock appears to be early or late and providing an output signal in accordance with the determination; and filtering said output signal and adjusting the local clock responsive to the filtered output signal to thereby synchronize the local clock to the symbol timing of the data signal.
Claim 13
Independent Claim
176 words
A method of synchronizing a local clock with symbol timing of an input data signal, comprising the steps of: obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to edge transitions of said local clock; phase shifting said clock by a piecewise continuous symmetrical time varying phase shifting function to provide a phase shifted clock signal and obtaining a third data sample of said data signal, responsive to an edge transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, wherein said third sampling instant varies for each symbol sample relative to said first and second sampling instants; determining, based on said first, second and third data samples, whether the clock appears to be early or late and providing an output signal in accordance with the determination; and filtering said output signal and adjusting the local clock responsive to the filtered output signal to thereby synchronize the local clock to the symbol timing of the data signal.
Claim 14
Dependent Claim
43 words
The method of claim 11 wherein said time varying phase shift is sufficient to enable said output signal to be provided with a mean amplitude substantially proportional to the phase error between the local clock and the symbol timing of the data signal.
Claim 15
Dependent Claim
40 words
The method of claim 11 wherein said time varying phase shift is selected from the group consisting of a sinusoidally varying phase shift, a phase shift varying as a sawtooth waveform, and a phase shift varying as a triangular wave.
Claim 16
Dependent Claim
39 words
The method of claim 11 wherein said first and second data samples are samples of consecutive symbols of said data signal and said first and second sampling instants correspond to edge transitions of consecutive pulses of said local clock.
Claim 17
Dependent Claim
43 words
The method of claim 11 , further comprising detecting a frequency error between said local clock and said symbol timing based on said output signal, generating a corresponding frequency error signal and adding it to said output signal prior to said filtering step.
Claim 18
Dependent Claim
135 words
The method of claim 12 wherein: said clock is determined to be early when said first data sample equals said data crossover sample and is unequal to said second data sample, said output signal being provided at a first level when said clock is determined to be early; said clock is determined to be late when said second and data crossover samples are equal and said first and data crossover samples are unequal, said output signal being provided at a second level when said clock is determined to be late; and said output signal is provided at a third level corresponding to a no-decision result when said first, second and data crossover samples are equal or said first and second data samples are equal to one another and are unequal to said data crossover sample.
Claim 19
Dependent Claim
215 words
An integrated circuit comprising a clock recovery circuit for synchronizing a local clock of a local clock generator with symbol timing of an input data signal, characterized in that said clock recovery circuit comprises: means for phase shifting said local clock by a time varying phase shift to provide a phase shifted clock signal, wherein said time varying phase shift is characterized by a piecewise continuous symmetrical function; sampling circuitry for obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to pulses of said local clock, and for obtaining a third sample of said data signal, responsive to a transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, said third sampling instant varying in time for each symbol sample relative to said first and second sampling instants; logic circuitry operative to determine, based on said first, second and third data samples, whether the clock appears to be early or late and to provide an output signal in accordance with the determination; and a filter, for filtering said output signal and providing the filtered signal to said local clock generator to adjust the local clock accordingly and thereby synchronize the local clock to the symbol timing.
Claim 20
Dependent Claim
215 words
An integrated circuit comprising a clock recovery circuit for synchronizing a local clock of a local clock generator with symbol timing of an input data signal, characterized in that said clock recovery circuit comprises: means for phase shifting said local clock by a time varying phase shift to provide a phase shifted clock signal, wherein said time varying phase shift is characterized by a piecewise continuous symmetrical function; sampling circuitry for obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to pulses of said local clock, and for obtaining a third sample of said data signal, responsive to a transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, said third sampling instant varying in time for each symbol sample relative to said first and second sampling instants; logic circuitry operative to determine, based on said first, second and third data samples, whether the clock appears to be early or late and to provide an output signal in accordance with the determination; and a filter, for filtering said output signal and providing the filtered signal to said local clock generator to adjust the local clock accordingly and thereby synchronize the local clock to the symbol timing.
Claim 21
Dependent Claim
44 words
The integrated circuit of claim 17 wherein said time varying phase shift is a phase shift selected from the group consisting of a sinusoidally varying phase shift, a phase shift varying as a sawtooth waveform, and a phase shift varying as a triangular wave.
Claim 22
Dependent Claim
217 words
A receiver for receiving an input data signal, comprising: a clock recovery circuit for synchronizing a local clock of a local clock generator with symbol timing of said input data signal, said clock recovery circuit including: means for phase shifting said local clock by a time varying phase shift to provide a phase shifted clock signal, wherein said time varying phase shift is characterized by a piecewise continuous symmetrical function; sampling circuitry for obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to pulses of said local clock, and for obtaining a third sample of said data signal, responsive to a transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, said third sampling instant varying in time for each symbol sample relative to said first and second sampling instants; logic circuitry operative to determine, based on said first, second and third data samples, whether the clock appears to be early or late and to provide an output signal in accordance with the determination; and a filter, for filtering said output signal and providing the filtered signal to said local clock generator to adjust the local clock accordingly and thereby synchronize the local clock to the symbol timing.
Claim 23
Dependent Claim
217 words
A receiver for receiving an input data signal, comprising: a clock recovery circuit for synchronizing a local clock of a local clock generator with symbol timing of said input data signal, said clock recovery circuit including: means for phase shifting said local clock by a time varying phase shift to provide a phase shifted clock signal, wherein said time varying phase shift is characterized by a piecewise continuous symmetrical function; sampling circuitry for obtaining first and second data samples of said data signal at respective first and second sampling instants corresponding to pulses of said local clock, and for obtaining a third sample of said data signal, responsive to a transition of said phase shifted clock signal, at a third sampling instant in between the first and second sampling instants, said third sampling instant varying in time for each symbol sample relative to said first and second sampling instants; logic circuitry operative to determine, based on said first, second and third data samples, whether the clock appears to be early or late and to provide an output signal in accordance with the determination; and a filter, for filtering said output signal and providing the filtered signal to said local clock generator to adjust the local clock accordingly and thereby synchronize the local clock to the symbol timing.
Claim 24
Dependent Claim
43 words
The receiver of claim 19 wherein said time varying phase shift is a phase shift selected from the group consisting of a sinusoidally varying phase shift, a phase shift varying as a sawtooth waveform, and a phase shift varying as a triangular wave.
References Cited (Backward Citations)
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