US4871975A
Expired / Lapsed
US
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Carrier recovery circuit for offset QPSK demodulators
Assignee: NEC Corp
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Filing: 1988-12-23
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Granted: 1989-10-03
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Expires: 2008-12-23
Abstract
Abstract A carrier recovery circuit comprises a voltage-controlled oscillator with a π/2 phase shifter coupled to it for generating carriers of quadrature phase relationship. First and second phase comparators respectively detect phase differences between an offset QPSK modulated signal and the carriers of the quadrature phase relationship. Signal from the first phase comparator is delayed by a 1/2 symbol duration and applied to one input of a quadri-phase detector having stable phase angles at π/4, (3/4)π, (5/4)π and (7/4)π radian and signal from the second phase comparator is applied to the other input of the quadri-phase detector. A bit timing recovery field (1010 . . . 1010) of the second channel is detected from the output of the second phase comparator. Signal from the quadri-phase detector is applied to a loop filter and thence to the voltage-controlled oscillator during the time when a bit timing recovery field (BTR) of the second channel is not still detected. To stabilize the operation of the carrier recovery loop of the circuit, the output of the second phase comparator from which that BTR is detected is briefly applied to the loop filter in response to the detection of a BTR of the second channel, instead of the signal from the quadri-phase detector.
Inventors
- 👤 Hizuru Nawata
- 👤 Susumu Otani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:36
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H04L27/0014; H04L2027/0024; H04L2027/0026; H04L2027/0028; H04L2027/0044; H04L2027/0053; H04L2027/0057; H04L2027/0063; H04L2027/0069; H04L7/00; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
270 words
A carrier recovery circuit for recovering a frequency reference for first and second channels of a received offset QPSK (quadrature phase shift keying) modulated signal, each of said channels having a carrier recovery field and a bit timing recovery field (BTR), the carrier recovery field of each of said channels and the BTR of said first channel having a series of binary digits of identical logic values and the BTR of said second channel having a series of binary digits of alternating logic values, comprising: means including a voltage-controlled oscillator and a π/2 phase shifter coupled to the oscillator for generating carriers of quadrature phase relationship; first and second phase comparators for respectively detecting phase differences between said first and second channels of said offset QPSK modulated signal and said carriers; delay means for introducing a delay of 1/2 symbol duration to a signal from one of said first and second phase comparators; quadri-phase detector means having stable phase angles at π/4, (3/4)π, (5/4)π and (7/4)π radian for receiving a signal from said delay means and a signal from said second phase comparator; BTR detector means connected to said second phase comparator for detecting the BTR of said second channel and generating a pulse upon the detection of said BTR; selecting means for selecting a signal from said quadri-phase detector means in the absence of said pulse and briefly selecting a signal from said second phase comparator in the presence of said pulse; and a loop filter for filtering the signal selected by said selecting means and supplying the filtered signal to said voltage-controlled oscillator as a frequency control signal.
Claim 2
Dependent Claim
270 words
A carrier recovery circuit for recovering a frequency reference for first and second channels of a received offset QPSK (quadrature phase shift keying) modulated signal, each of said channels having a carrier recovery field and a bit timing recovery field (BTR), the carrier recovery field of each of said channels and the BTR of said first channel having a series of binary digits of identical logic values and the BTR of said second channel having a series of binary digits of alternating logic values, comprising: means including a voltage-controlled oscillator and a π/2 phase shifter coupled to the oscillator for generating carriers of quadrature phase relationship; first and second phase comparators for respectively detecting phase differences between said first and second channels of said offset QPSK modulated signal and said carriers; delay means for introducing a delay of 1/2 symbol duration to a signal from one of said first and second phase comparators; quadri-phase detector means having stable phase angles at π/4, (3/4)π, (5/4)π and (7/4)π radian for receiving a signal from said delay means and a signal from said second phase comparator; BTR detector means connected to said second phase comparator for detecting the BTR of said second channel and generating a pulse upon the detection of said BTR; selecting means for selecting a signal from said quadri-phase detector means in the absence of said pulse and briefly selecting a signal from said second phase comparator in the presence of said pulse; and a loop filter for filtering the signal selected by said selecting means and supplying the filtered signal to said voltage-controlled oscillator as a frequency control signal.
Claim 3
Dependent Claim
233 words
A carrier recovery circuit as claimed in claim 1, further comprising: envelope detector means connected to the outputs of said firsta nd second comparators for detecting the carrier recovery field of at least one of said first and second channels; initial phase error estimator means connected to said first and second phase comparators for estimating an initial phase error of a closed loop formed bys aid carrier recovery circuit with respect to a signal phase of said offset QPSK signal; frequency error estimator means for deriving from the estimated initial phase error a signal representative of a frequency offset of said carriers with respect to a frequency of said QPSK signal; variable phase shifting means for introducing a constant phase shift of (π/4) radian and a variable amount of phase shift equal to the estimated initial phase error to said carriers in response to the detection of a carrier recovery field by said envelope detector means; second selecting means for selecting a signal from said second phase comparator when said carrier recovery field is not detected by said envelope detector means and selecting a signal from said loop filter when said carrier recovery field is detected by said envelope detector means; and means for combining the signal selected by said second selecting means with said frequency offset representative signal and supplying the combined signals to said voltage-controlled oscillator as said frequency control signal.
Claim 4
Dependent Claim
81 words
A carrier recovery circuit as claimed in claim 1, wherein said BTR detector means comprises a low-pass filter for filtering a signal from said second phase comparator, a comparator for generating a signal when a signal filtered by said low-pass filter decreases below a predetermined level, and means for generating said pulse in response to a trailing edge of said signal from said comparator and applying said pulse to said selecting means as an indication of the detection of said BTR.
Claim 5
Dependent Claim
42 words
A carrier recovery circuit as claimed in claim 3, wherein said BTR detector means further comprises a squaring circuit for squaring the signal filtered by said low-pass filter and applying the squared signal to said comparator for comparison with said predetermined level.
Claim 6
Dependent Claim
76 words
A carrier recovery circuit as claimed in claim 2, wherein said initial phase error is represented by 2πΔf/k, where k represents a loop gain of said closed loop and Δf represents the amount of said frequency offset, and wherein said initial phase error estimator means includes low-pass filters for filtering signals from said first and second phase comparators and calculates tan -1 α/β, where α and β represent respectively the signals filtered by said low-pass filters.
References Cited (Backward Citations)
US4704582A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |