US5719908A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital/analog bit synchronizer
Assignee: Unisys Corp
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Filing: 1995-07-19
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Granted: 1998-02-17
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Expires: 2015-07-19
Abstract
Abstract A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.
Inventors
- 👤 Roy Edgar Greeff
- 👤 Glenn Arthur Arbanas
- 👤 Bruce Howard Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:04
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L7/10; H03L7/12; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
154 words
A high speed bit synchronizer for generating a coherent clock synchronized with a received digital data stream, comprising: a digital phase detector having an input for receiving said digital data stream and producing a clocked data output, first summing means having a first input coupled to the clocked data output of said digital phase detector, offset eliminating means having an input coupled to the phase detector and a correction signal output coupled to a second input of said first summing means, a loop filter, said first summing means having positive inputs and a summed voltage output coupled to said loop filter, a voltage controlled oscillator having an input coupled to the filtered summed voltage output and having the coherent clock with a steady state phase offset, and the output of said first summing means having a linear output phase offset S-curve around the lock point of said phase detector, whereby seeking is substantially eliminated.
Claim 2
Dependent Claim
154 words
A high speed bit synchronizer for generating a coherent clock synchronized with a received digital data stream, comprising: a digital phase detector having an input for receiving said digital data stream and producing a clocked data output, first summing means having a first input coupled to the clocked data output of said digital phase detector, offset eliminating means having an input coupled to the phase detector and a correction signal output coupled to a second input of said first summing means, a loop filter, said first summing means having positive inputs and a summed voltage output coupled to said loop filter, a voltage controlled oscillator having an input coupled to the filtered summed voltage output and having the coherent clock with a steady state phase offset, and the output of said first summing means having a linear output phase offset S-curve around the lock point of said phase detector, whereby seeking is substantially eliminated.
Claim 3
Dependent Claim
102 words
A high speed bit synchronizer as set forth in claim 1 which further includes a digital lock detector having an input coupled to said digital data stream and an output coupled to a second summing means, said second summing means having a second input coupled to the output of said offset eliminating means, a low pass filter having an input coupled to the output of said second summing means for producing an adjusted error signal output, and a comparator coupled to receive said adjusted error signal output for producing a lock indication signal at the true lock point for said phase detector.
Claim 4
Dependent Claim
52 words
A high speed bit synchronizer as set forth in claim 1 wherein said digital phase detector comprises a flip-flop having a clocked data output coupled to a first exclusive OR gate, said first exclusive OR gate having a second input coupled to said data stream and having a phase error signal output.
Claim 5
Dependent Claim
71 words
A high speed bit synchronizer as set forth in claim 3 wherein said digital phase detector further comprises a third summing means coupled to the first input of the first summing means and to said exclusive OR gate, and the output of said offset eliminating means being coupled to the second input of said first summing means for producing a phase error correction signal adjusted for the occurrence of unsymmetrical data.
Claim 6
Dependent Claim
53 words
A high speed bit synchronizer as set forth in claim 4 wherein said offset eliminating means comprises a second flip-flop having a clocked data output and a clock data input, and a second exclusive OR gate having an input coupled to the output of said second flip-flop for producing an offset correction signal.
Claim 7
Dependent Claim
53 words
A high speed bit synchronizer as set forth in claim 5 wherein said offset eliminating means further includes gating means coupled to the second exclusive OR gate, and fourth summing means coupled to the output of said gating means for producing said correction signal output at the output of said offset eliminating means.
Claim 8
Dependent Claim
62 words
A high speed bit synchronizer as set forth in claim 1 wherein said digital phase detector comprises a third summing means coupled to said first summing means which comprises a digital summing circuit for producing a digital adjusted phase error signal, and wherein said voltage control oscillator comprises a digital voltage controlled oscillator coupled to the output of said digital summing circuit.
Claim 9
Dependent Claim
34 words
A high speed bit synchronizer as set forth in claim 7 wherein said offset eliminating means comprises a high-low digital counter having a digital output coupled to an input of said digital summing circuit.
Claim 10
Dependent Claim
39 words
A high speed bit synchronizer as set forth in claim 1 which further comprises lock detector means coupled to the coherent clock and to said digital data stream for indicating a true lock point on said phase offset S-curve.
Claim 11
Dependent Claim
27 words
A high speed bit synchronizer as set forth in claim 9 wherein said lock detector means comprises a fifth summing means coupled to said second summing means.
Claim 12
Dependent Claim
37 words
A high speed bit synchronizer as set forth in claim 10 wherein said lock detector means further comprises a third flip-flop coupled to a third exclusive OR gate having an output coupled to said fifth summing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-16 | 2001-08-18 | 2002-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-16 | 2005-08-18 | 2006-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-16 | 2009-08-18 | 2010-02-17 | $7700.00 | Window Closed / Lapsed |