US5608731A
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Closed loop clock recovery for synchronous residual time stamp
Assignee: Transwitch Corp
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Filing: 1995-03-31
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Granted: 1997-03-04
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Expires: 2015-03-31
Abstract
Abstract An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.
Inventors
- 👤 Daniel C. Upp
- 👤 Dan H. Wolaver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:54
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0632; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5638; H04L2012/5646; H04L2012/5652; H04L2012/5672; H04L2012/5674
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
164 words
An apparatus for the recovery of a source clock which has been encoded utilizing the source clock and a system reference clock according to a synchronous residual time stamp (SRTS) algorithm, where the encoding generates residual time stamp (RTS) values which are obtained by said apparatus as incoming RTS values, said apparatus comprising: a) controllable oscillator means for generating a destination node clock; b) means for generating local residual time stamp related values, said means for generating utilizing said destination node clock and the system reference clock; and c) control signal generating means coupled in a feedback loop between said means for generating and said controllable oscillator means, said control signal generating means including first comparison means for comparing incoming RTS-related values which are related to the incoming RTS values to the local RTS-related values, said control signal generating means for generating feedback control signals to said controllable oscillator means which are used by said controllable oscillator means to adjust said destination node clock.
Claim 2
Independent Claim
164 words
An apparatus for the recovery of a source clock which has been encoded utilizing the source clock and a system reference clock according to a synchronous residual time stamp (SRTS) algorithm, where the encoding generates residual time stamp (RTS) values which are obtained by said apparatus as incoming RTS values, said apparatus comprising: a) controllable oscillator means for generating a destination node clock; b) means for generating local residual time stamp related values, said means for generating utilizing said destination node clock and the system reference clock; and c) control signal generating means coupled in a feedback loop between said means for generating and said controllable oscillator means, said control signal generating means including first comparison means for comparing incoming RTS-related values which are related to the incoming RTS values to the local RTS-related values, said control signal generating means for generating feedback control signals to said controllable oscillator means which are used by said controllable oscillator means to adjust said destination node clock.
Claim 3
Dependent Claim
27 words
An apparatus according to claim 1, wherein: said local RTS-related values are actual local RTS values, and said incoming RTS-related values are said actual incoming RTS values.
Claim 4
Dependent Claim
143 words
An apparatus according to claim 1, where said source clock was divided by a value N and said system reference clock was divided by a value x and fed to a P-bit counter in generating said RTS values, wherein: said means for generating local residual time stamp related values includes a first divider means for dividing said destination node clock by said value N, a second dividing means for dividing the system reference clock by said value x to provide a system related clock, a mod-2 P counting means for counting cycles of said system related clock, and a latch means coupled to said mod-2 P counting means and to said first divider means, said latch means for latching P-bit values of said mod-2 P counting means whenever said first divider means generates an output pulse, said P-bit values being local RTS values.
Claim 5
Dependent Claim
27 words
An apparatus according to claim 1, wherein: said controllable oscillator means is a digitally controllable oscillator means, and said feedback control signals are digital feedback control signals.
Claim 6
Dependent Claim
133 words
An apparatus according to claim 4, wherein: said controllable oscillator means comprises a first summing means having a scale offset input for summing said digital feedback control signals with said scale offset input to provide a first sum, a second summing means having a second sum output and carry output, a latch means coupled to said second summing means for receiving said second sum output and for providing said second sum output to said second summing means for summing with said first sum, and a dividing means for dividing a fast clock by a first value when said carry output is a first value, and for dividing the fast clock by a second value when said carry output is a second value, an output of said dividing means providing said destination node clock.
Claim 7
Dependent Claim
28 words
An apparatus according to claim 5, wherein: said fast clock is a substantially 48.636 MHz clock, and said first value is thirty-one, and said second value is thirty-two.
Claim 8
Dependent Claim
85 words
An apparatus according to claim 1, wherein: said control signal generating means comprises a second comparison means for comparing a new local RTS values to previous local RTS values and generating a delta local RTS values, said delta local RTS values constituting said local RTS-related values, and said control signal generating means further comprises a third comparison means for comparing new RTS incoming values to previous RTS incoming values and generating delta incoming RTS values, said delta incoming RTS values constituting said incoming RTS-related values.
Claim 9
Dependent Claim
24 words
An apparatus according to claim 7, wherein: said second comparison means comprises a mod-16 comparator, and said third comparison means comprises a mod-16 comparator.
Claim 10
Dependent Claim
25 words
An apparatus according to claim 7, wherein: said first comparator means generates error signals which constitute said feedback control signals to said controllable oscillator means.
Claim 11
Dependent Claim
36 words
An apparatus according to claim 7, wherein: said first comparator means generates error signals, and said control signal generating means further comprises filter means for filtering said error signals and generating therefrom said feedback control signals.
Claim 12
Dependent Claim
27 words
An apparatus according to claim 7, wherein: said controllable oscillator means is a digitally controllable oscillator means, and said feedback control signals are digital feedback control signals.
Claim 13
Dependent Claim
134 words
An apparatus according to claim 11, wherein: said controllable oscillator means comprises a first summing means having a scale offset input for summing said digital feedback control signals with said scale offset input to provide a first sum, a second summing means having a second sum output and carry output, a latch means coupled to said second summing means for receiving said second sum output and for providing said second sum output to said second summing means for summing with said first sum, and a first dividing means for dividing a fast clock by a first value when said carry output is a first value, and for dividing the fast clock by a second value when said carry output is a second value, an output of said dividing means providing said destination node clock.
Claim 14
Dependent Claim
28 words
An apparatus according to claim 12, wherein: said fast clock is a substantially 48.636 MHz clock, and said first value is thirty-one, and said second value is thirty-two.
Claim 15
Dependent Claim
143 words
An apparatus according to claim 13, where said source clock was divided by a value N and said system reference clock was divided by a value x and fed to a P-bit counter in generating said RTS values, wherein: said means for generating local residual time stamp related values includes a second dividing means for dividing said destination node clock by said value N, a third dividing means for dividing the system reference clock by said value x to provide a system related clock, a mod-2 P counting means for counting cycles of said system related clock, and a latch means coupled to said mod-2 P counting means and to said second divider means, said latch means for latching P-bit values of said mod-2 P counting means whenever said second divider means generates an output pulse, said P-bit values being local RTS values.
Claim 16
Independent Claim
310 words
A system in a packet-based telecommunications network for generating at a destination node a destination clock signal equivalent to a source clock signal of the source node, the destination node and source node having a common network clock, said system comprising: a) at the source node, first dividing means for dividing said source clock signal by a factor of an integer N to form residual time stamp periods; b) at the source node, first counting means coupled to the network clock for counting network clock cycles modulo 2 P ; c) at the source node, transmitting means, responsive to said residual time stamp periods and the count of said first counting means, for transmitting over the telecommunications network a residual time stamp at the end of each residual time stamp period, said residual time stamp being equal to the modulo 2 P count of network clock cycles at that time; d) at the destination node, a controllable oscillator means for generating said destination node clock signal; e) at the destination node, means for generating a local residual time stamp, said means for generating including second dividing means for dividing said destination node clock signal by a factor of said integer N, and second counting means coupled to the network clock for counting network clock cycles modulo 2 P ; and f) at the destination node, control signal generating means coupled in a feedback loop between said means for generating and said controllable oscillator means, said control signal generating means including first comparison means for comparing a first indication related to said residual time stamp transmitted over the telecommunications network to a second indication related to said local residual time stamp, said control signal generating means for generating feedback control signals to said controllable oscillator means which are used by said controllable oscillator means to adjust said destination node clock signal.
Claim 17
Independent Claim
310 words
A system in a packet-based telecommunications network for generating at a destination node a destination clock signal equivalent to a source clock signal of the source node, the destination node and source node having a common network clock, said system comprising: a) at the source node, first dividing means for dividing said source clock signal by a factor of an integer N to form residual time stamp periods; b) at the source node, first counting means coupled to the network clock for counting network clock cycles modulo 2 P ; c) at the source node, transmitting means, responsive to said residual time stamp periods and the count of said first counting means, for transmitting over the telecommunications network a residual time stamp at the end of each residual time stamp period, said residual time stamp being equal to the modulo 2 P count of network clock cycles at that time; d) at the destination node, a controllable oscillator means for generating said destination node clock signal; e) at the destination node, means for generating a local residual time stamp, said means for generating including second dividing means for dividing said destination node clock signal by a factor of said integer N, and second counting means coupled to the network clock for counting network clock cycles modulo 2 P ; and f) at the destination node, control signal generating means coupled in a feedback loop between said means for generating and said controllable oscillator means, said control signal generating means including first comparison means for comparing a first indication related to said residual time stamp transmitted over the telecommunications network to a second indication related to said local residual time stamp, said control signal generating means for generating feedback control signals to said controllable oscillator means which are used by said controllable oscillator means to adjust said destination node clock signal.
Claim 18
Dependent Claim
58 words
A system according to claim 15, wherein: said first indication related to said residual time stamp transmitted over the telecommunications network is said residual time stamp transmitted over the telecommunications network, and said second indication related to said local residual time stamp is a local RTS value generated by said means for generating a local residual time stamp.
Claim 19
Dependent Claim
88 words
A system according to claim 15, wherein: said first indication related to said residual time stamp transmitted over the telecommunications network is a first comparison between a first value of a residual time stamp transmitted over the telecommunications network and a previous second value of a residual time stamp transmitted over the telecommunications network, and said second indication related to said local residual time stamp is a second comparison between a third value of a local time stamp and a fourth value of a previous local time stamp.
Claim 20
Dependent Claim
65 words
A system according to claim 17, wherein: said integer N is 3008, said modulo 2 P count is a modulo sixteen count, said control signal generating means comprises a second comparison means for conducting said first comparison, and a third comparison means for conducting said second comparison, and said second comparison means comprises a mod-16 comparator, and said third comparison means comprises a mod-16 comparator.
Claim 21
Dependent Claim
25 words
A system according to claim 15, wherein: said first comparison means generates error signals which constitute said feedback control signals to said controllable oscillator means.
Claim 22
Dependent Claim
36 words
A system according to claim 15, wherein: said first comparator means generates error signals, and said control signal generating means further comprises filter means for filtering said error signals and generating therefrom said feedback control signals.
Claim 23
Dependent Claim
27 words
A system according to claim 15, wherein: said controllable oscillator means is a digitally controllable oscillator means, and said feedback control signals are digital feedback control signals.
Claim 24
Dependent Claim
133 words
A system according to claim 21, wherein: said controllable oscillator means comprises a first summing means having a scale offset input for summing said digital feedback control signals with said scale offset input to provide a first sum, a second summing means having a second sum output and carry output, a latch means coupled to said second summing means for receiving said second sum output and for providing said second sum output to said second summing means for summing with said first sum, and a dividing means for dividing a fast clock by a first value when said carry output is a first value, and for dividing the fast clock by a second value when said carry output is a second value, an output of said dividing means providing said destination node clock.
Claim 25
Independent Claim
140 words
A method for recovering at a destination node a source clock which has been encoded utilizing the source clock and a system reference clock according to a synchronous residual time stamp (SRTS) algorithm, where the encoding generates residual time stamp (RTS) values which are obtained by a destination node as incoming RTS values, said method comprising: a) at the destination node, generating local residual time stamp related values by utilizing a controllable destination node clock and the system reference clock; b) comparing indications relating to the incoming RTS values to indications related to the local RTS related values, and obtaining therefrom a comparison indication; c) using said comparison indication to generate a control signal; and d) feeding back said control signal to the controllable destination node clock in order to control the output frequency of the controllable destination node clock.
Claim 26
Independent Claim
140 words
A method for recovering at a destination node a source clock which has been encoded utilizing the source clock and a system reference clock according to a synchronous residual time stamp (SRTS) algorithm, where the encoding generates residual time stamp (RTS) values which are obtained by a destination node as incoming RTS values, said method comprising: a) at the destination node, generating local residual time stamp related values by utilizing a controllable destination node clock and the system reference clock; b) comparing indications relating to the incoming RTS values to indications related to the local RTS related values, and obtaining therefrom a comparison indication; c) using said comparison indication to generate a control signal; and d) feeding back said control signal to the controllable destination node clock in order to control the output frequency of the controllable destination node clock.
Claim 27
Dependent Claim
55 words
A method according to claim 23, wherein: said indications relating to the incoming RTS values are difference values between a present incoming RTS value and a previous incoming RTS value, and said indications related to the local RTS related values are difference values between a present local RTS value and a previous local RTS value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |