Patent US5695722A successfully refreshed from Google Patents.
US5485484A
Expired / Lapsed
US
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Digitally implemented phase and lock indicators for a bit synchronizer
Assignee: Unisys Corp
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Filing: 1993-12-21
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Granted: 1996-01-16
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Expires: 2013-12-21
Abstract
Abstract A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.
Inventors
- 👤 Bruce H. Williams
- 👤 Glenn A. Arbanas
- 👤 Roy E. Greeff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:56
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L7/10; H03L7/12; H04; H04L; H04L7/00; H04L7/02; H04L7/033; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
206 words
A variable rate bit synchronizing circuit for receiving incoming data and for synchronizing a voltage controlled oscillator with a clock rate of the incoming data, comprising: digital phase detector means having a pair of inputs connected to the incoming data and to a data rate clock for producing a pair of digital output signals, first summing means coupled to the digital outputs from said digital phase detector means, first filter means coupled to the output of said first summing means for producing a phase error signal output, a voltage control oscillator having an input coupled to the output of said filter means for producing a VCO clock output synchronized with the incoming data, a divider circuit connected in series between said VCO clock output and said digital phase detector means, digital lock detector means having inputs connected to said incoming data and to said VCO clock output from said voltage controlled oscillator and to said divider circuit for producing a pair of digital lock detection output signals, second summing means coupled to the digital outputs from said digital lock detector means, and second filter means coupled to the output of said second summing means for producing a lock detector signal indicative of a predetermined lock condition.
Claim 2
Dependent Claim
206 words
A variable rate bit synchronizing circuit for receiving incoming data and for synchronizing a voltage controlled oscillator with a clock rate of the incoming data, comprising: digital phase detector means having a pair of inputs connected to the incoming data and to a data rate clock for producing a pair of digital output signals, first summing means coupled to the digital outputs from said digital phase detector means, first filter means coupled to the output of said first summing means for producing a phase error signal output, a voltage control oscillator having an input coupled to the output of said filter means for producing a VCO clock output synchronized with the incoming data, a divider circuit connected in series between said VCO clock output and said digital phase detector means, digital lock detector means having inputs connected to said incoming data and to said VCO clock output from said voltage controlled oscillator and to said divider circuit for producing a pair of digital lock detection output signals, second summing means coupled to the digital outputs from said digital lock detector means, and second filter means coupled to the output of said second summing means for producing a lock detector signal indicative of a predetermined lock condition.
Claim 3
Dependent Claim
29 words
A variable rate bit synchronizer as set forth in claim 1 wherein said first filter means and said voltage controlled oscillator comprise analog devices for receiving analog input signals.
Claim 4
Dependent Claim
31 words
A variable rate bit synchronizer as set forth in claim 2 wherein said first summing circuit comprises an analog output device for receiving digital signals from said digital phase detector means.
Claim 5
Dependent Claim
68 words
A variable rate bit synchronizer as set forth in claim 2 wherein said second summing means comprises an analog output device and said second filter means comprises analog low pass filter means coupled to the output of said second summing means, and an analog comparator coupled to the output of said analog low pass filter means for producing a lock detection signal after a reference voltage is exceeded.
Claim 6
Dependent Claim
49 words
A bit synchronizing circuit as set forth in claim 4 which further includes sweep circuit means coupled between the output of said analog comparator and an input to said voltage controlled oscillator for resolving frequency uncertainties in said bit synchronizing circuit when said predetermined lock condition does not exist.
Claim 7
Dependent Claim
41 words
A variable rate bit synchronizing circuit as set forth in claim 1 wherein said digital phase detector means and said digital lock detector means comprise a plurality of flip-flops and logic gates implemented on a single gate array logic semiconductor chip.
References Cited (Backward Citations)
US4419760A
Cited
US4617520A
Cited
US4837781A
Cited
US4780893A
Cited
US5233636A
Cited
US5121071A
Cited
US5301196A
Cited
US5313499A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |