US4419760A
Expired / Lapsed
US
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Augmented phase-locked loop for very wide range acquisition and method therefor
Assignee: Motorola Solutions Inc
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Filing: 1982-01-29
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Granted: 1983-12-06
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Expires: 2002-01-29
Abstract
Abstract An augmented phase-locked loop for use with a data communication system in which the data is encoded into a plurality of symbol signals such that the channel on which transmission occurs is switched at a data clock rate between symbol signals and such that two like symbol signals cannot appear successively. The coincidental transitions between symbol signals are detected and are used to lock a phase-locked loop. If the integrated signal from a transition detector is greater than integration of the signal level of the pluses on each incoming channel at the frequency of the loop locking to a subharmonic is detected and causes a sweep circuit to drive an oscillator to sweep until the phase-locked loop locks on the correct data clock frequency. The frequency to which the loop is locked is used to clock a successive sampling of each input so that if the loop is locked on a harmonic of the correct data clock, the sequential repetition of a symbol signal on a channel is detected and is used to force an oscillator to sweep until the phase-locked loop is locked to the correct data clock frequency.
Inventors
- 👤 John E. Bjornholt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:15
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
268 words
A phase locked loop for use with a system of data communications having a plurality of transmission channels and providing a sequence of symbol signals along the plurality of channels such that no channel is used for the transmission of symbol signals twice in succession and such that the rising and falling transitions of a symobl signal on one of the plurality of channels respectively coincide with the falling transition of the signal on one other of the plurality of channels and the rising transition of a symbol signal on one other of the plurality of channels, comprising: a plurality of channel inputs; means for detecting the coincidental symbol signal transitions having a plurality of inputs coupled to said plurality of channel inputs and having an output; means for controlling an oscillator having a first input coupled to said output of said means for detecting the coincidental symbol signal transitions, having a second input, having a third input and having an output; an oscillator having an input coupled to said output of said means for controlling an oscillator having an output coupled to said third input of said means for controlling an oscillator; and means for comparing the symbol signals with an oscillating signal and with the coincidental transitions of the symbol signals having a plurality of inputs coupled to said plurality of channel inputs, having an input coupled to said output of said means for detecting the coincidental symbol signal transitions, having an input coupled to said output of said oscillator, and having an output coupled to said second input of said means for controlling an oscillator.
Claim 2
Dependent Claim
268 words
A phase locked loop for use with a system of data communications having a plurality of transmission channels and providing a sequence of symbol signals along the plurality of channels such that no channel is used for the transmission of symbol signals twice in succession and such that the rising and falling transitions of a symobl signal on one of the plurality of channels respectively coincide with the falling transition of the signal on one other of the plurality of channels and the rising transition of a symbol signal on one other of the plurality of channels, comprising: a plurality of channel inputs; means for detecting the coincidental symbol signal transitions having a plurality of inputs coupled to said plurality of channel inputs and having an output; means for controlling an oscillator having a first input coupled to said output of said means for detecting the coincidental symbol signal transitions, having a second input, having a third input and having an output; an oscillator having an input coupled to said output of said means for controlling an oscillator having an output coupled to said third input of said means for controlling an oscillator; and means for comparing the symbol signals with an oscillating signal and with the coincidental transitions of the symbol signals having a plurality of inputs coupled to said plurality of channel inputs, having an input coupled to said output of said means for detecting the coincidental symbol signal transitions, having an input coupled to said output of said oscillator, and having an output coupled to said second input of said means for controlling an oscillator.
Claim 3
Dependent Claim
71 words
A phase-locked loop as recited in claim 1 wherein said means for comparing symbol signals comprises means for detecting successive of symbol signals having an input coupled to said output of said oscillator, having a plurality of inputs, one each of said plurality of inputs being coupled to one of said plurality of channel inputs, and having an output coupled to said second input of said means for controlling an oscillator.
Claim 4
Dependent Claim
145 words
A phase-locked loop as recited in claim 1 wherein said means for comparing symbol signals comprises: a coincidental transition symbol signal integrator having an input coupled to said output of said means for detecting the coincidental symbol signal transitions and having an output; a plurality of symbol signal integrators, each of said plurality of symbol signal integrators having an input coupled to one of said plurality of channel inputs, and each of said plurality of symbol signal integrators having an output; and means for comparing integrated signal levels, said means for comparing integrated signal levels having a plurality of inputs one of said plurality of inputs being coupled to each of said outputs of said symbol signal integrators, having an input coupled to said coincidental transition symbol signal integrator, and having an output coupled to said second input of said means for controlling an oscillator.
Claim 5
Dependent Claim
621 words
A phase locked loop for use with a system of data communications having a plurality of transmission channels and providing a sequence of symbol signals along the plurality of channels such that no channel is used for the transmission of symbol signals twice in succession and such that the rising and falling transitions of a symbol signal on one of the plurality of channels respectively coincide with the falling transition of a signal on one other of the plurality of channels and the rising transition of a symbol signal on one other of the plurality of channels, comprising: a plurality of channel inputs; means for detecting the coincidental symbol signal transitions having a plurality of inputs coupled to said plurality of channel inputs and having an output; a phase detector having a first input coupled to said output of said means for detecting the coincidental symbol signal transitions, having a second input and having an output; a loop filter having an input coupled to said output of said phase detector, having a first output and having a second output; a summing circuit having a first input coupled to said output of said loop filter, having a second input and having an output; a voltage controlled oscillator having an input coupled to said output of said summing circuit and having an output; a sweep circuit having a first input coupled to said second output of said loop filter, having a second input and having an output coupled to said second input of said summing circuit; means for detecting successive repetitions having an input coupled to said output of said voltage controlled oscillator, having a plurality of inputs, one each of said plurality of inputs being coupled to one of said plurality of channel inputs, and having an output coupled to said second input of said sweep circuit; a first integrate and dump circuit having a first input coupled to said output of said means for detecting coincidental symbol signal transitions, having a second input coupled to said output of said voltage controlled oscillator, and having an output; a second integrate and dump circuit having a first input coupled to a first of said plurality of channel inputs, having a second input coupled to said output of said voltage controlled oscillator and having an output; a third integrate and dump circuit having a first input coupled to a second of said plurality of channel inputs, having a second input coupled to said output of said voltage controlled oscillator and having an output; a fourth integrate and dump circuit having a first input coupled to a third of said plurality of channel inputs, having a second input coupled to said output of said voltage controlled oscillator and having an output; a first comparator having a first input coupled to said output of said second integrate and dump circuit, having a second input coupled to said output of said first integrate and dump circuit, and having an output; a second comparator having a first input coupled to said output of said third integrate and dump circuit, having a second input coupled to said output of said first integrate and dump circuit, and having an output; a third comparator having a first input coupled to said output of said fourth integrate and dump circuit, having a second input coupled to said output of said first integrate and dump circuit, and having an output; and a logic gate having a first input coupled to said output of said first comparator, having a second input coupled to said output of said second comparator, having a third input coupled to said output of said third comparator, and having an output coupled to said second input of said sweep circuit.
Claim 6
Dependent Claim
621 words
A phase locked loop for use with a system of data communications having a plurality of transmission channels and providing a sequence of symbol signals along the plurality of channels such that no channel is used for the transmission of symbol signals twice in succession and such that the rising and falling transitions of a symbol signal on one of the plurality of channels respectively coincide with the falling transition of a signal on one other of the plurality of channels and the rising transition of a symbol signal on one other of the plurality of channels, comprising: a plurality of channel inputs; means for detecting the coincidental symbol signal transitions having a plurality of inputs coupled to said plurality of channel inputs and having an output; a phase detector having a first input coupled to said output of said means for detecting the coincidental symbol signal transitions, having a second input and having an output; a loop filter having an input coupled to said output of said phase detector, having a first output and having a second output; a summing circuit having a first input coupled to said output of said loop filter, having a second input and having an output; a voltage controlled oscillator having an input coupled to said output of said summing circuit and having an output; a sweep circuit having a first input coupled to said second output of said loop filter, having a second input and having an output coupled to said second input of said summing circuit; means for detecting successive repetitions having an input coupled to said output of said voltage controlled oscillator, having a plurality of inputs, one each of said plurality of inputs being coupled to one of said plurality of channel inputs, and having an output coupled to said second input of said sweep circuit; a first integrate and dump circuit having a first input coupled to said output of said means for detecting coincidental symbol signal transitions, having a second input coupled to said output of said voltage controlled oscillator, and having an output; a second integrate and dump circuit having a first input coupled to a first of said plurality of channel inputs, having a second input coupled to said output of said voltage controlled oscillator and having an output; a third integrate and dump circuit having a first input coupled to a second of said plurality of channel inputs, having a second input coupled to said output of said voltage controlled oscillator and having an output; a fourth integrate and dump circuit having a first input coupled to a third of said plurality of channel inputs, having a second input coupled to said output of said voltage controlled oscillator and having an output; a first comparator having a first input coupled to said output of said second integrate and dump circuit, having a second input coupled to said output of said first integrate and dump circuit, and having an output; a second comparator having a first input coupled to said output of said third integrate and dump circuit, having a second input coupled to said output of said first integrate and dump circuit, and having an output; a third comparator having a first input coupled to said output of said fourth integrate and dump circuit, having a second input coupled to said output of said first integrate and dump circuit, and having an output; and a logic gate having a first input coupled to said output of said first comparator, having a second input coupled to said output of said second comparator, having a third input coupled to said output of said third comparator, and having an output coupled to said second input of said sweep circuit.
Claim 7
Independent Claim
201 words
A method for providing a data clock signal output of an oscillator, the data clock signal being in phase with and at the same frequency as a sequence of symbol signals transmitted along a plurality of channels such that no channel is used for transmission twice in succession such that the rising and falling transitions of a symbol signal on one of the plurality of channels respectively coincide with the falling portion of a symbol signal on one other of the plurality of channels and the rising transition of a symbol signal on one other of the plurality of channels, comprising the steps of: forming a series of pulses indicative of the frequency of the coincidental transitions; producing a signal representative of any phase difference between said series of pulses and the data clock signal; driving the oscillator with said signal representative of any phase difference; comparing the frequency of the data clock signal with the rate of repetition of the sequence of symbol signals and with the frequency of said series of pulses indicative of the frequency of the coincidental transitions to produce a sweep enabling signal; and using said sweep enabling signal to control the sweeping of the oscillator.
Claim 8
Independent Claim
201 words
A method for providing a data clock signal output of an oscillator, the data clock signal being in phase with and at the same frequency as a sequence of symbol signals transmitted along a plurality of channels such that no channel is used for transmission twice in succession such that the rising and falling transitions of a symbol signal on one of the plurality of channels respectively coincide with the falling portion of a symbol signal on one other of the plurality of channels and the rising transition of a symbol signal on one other of the plurality of channels, comprising the steps of: forming a series of pulses indicative of the frequency of the coincidental transitions; producing a signal representative of any phase difference between said series of pulses and the data clock signal; driving the oscillator with said signal representative of any phase difference; comparing the frequency of the data clock signal with the rate of repetition of the sequence of symbol signals and with the frequency of said series of pulses indicative of the frequency of the coincidental transitions to produce a sweep enabling signal; and using said sweep enabling signal to control the sweeping of the oscillator.
Claim 9
Dependent Claim
71 words
A method for providing a data clock signal as recited in claim 5 wherein said comparing step comprises the steps of: sampling the symbol signals on each of the channels at the rate of the data clock signal; determining whether one symbol signal is sampled twice in succession; and outputting a sweep enabling signal when the result of said determining step is that one symbol signal is sampled twice in succession.
Claim 10
Dependent Claim
77 words
A method for providing a data clock signal as recited in claim 5 wherein said comparing step comprises the steps of: separately integrating said series of pulses and the symbol signals for each of the plurality of channels for the period of the data clock signal; and producing the sweep enabling signal when the result of integrating said series of pulses exceeds the result of integrating the symbol signals in any one of the plurality of channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |