US5121071A
Expired / Lapsed
US
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Lock detector for unbalanced QPSK demodulators
Assignee: Lockheed Martin Corp
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Filing: 1991-07-31
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Granted: 1992-06-09
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Expires: 2011-07-31
Abstract
Abstract A lock detector circuit (60) for demodulators of UQPSK signals I and Q has signal processing circuits for forming the signals: A=6I.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4 ; B=4(I.sup.2 -Q.sup.2). A switch (19) is provided for coupling either signal A or signal B to the output (20) of the detector circuit, depending on the value of the signal ratio Q/I. In an alternative embodiment, a summing circuit adds signal A and signal B, and directs the sum to the detector output (20). The resulting output signal is constant under lock conditions, and oscillates when the demodulator is unlocked. This output signal is directed through a comparator (49) to the sweep circuit (43) controlling demodulator VCO (42), and causes the demodulator to remain in the locked condition. The lock detector circuit is effective for any value of Q/I, and utilizes only three analog multiplier circuits.
Inventors
- 👤 Lawrence R. Kelly
- 👤 Geoffrey S. Waugh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:19
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
136 words
A lock detector circuit for producing a lock detection signal from output signals I and Q generated by a demodulator of a UQPSK signal, said circuit comprising: first signal processing means for receiving said signals I and Q to produce a signal A at a first terminal: A=KI.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4, where K is a constant value; second signal processing means for receiving said signals I and Q to produce the signal B at a second terminal: B=4(I.sup.2 -Q.sup.2); and a switch having a plurality of switching positions, said switch coupling the control circuits of said demodulator to said first terminal in a first switching position, and coupling the control circuits of said demodulator to said second terminal in a second switching position, whereby said control circuits are responsive to said signal A or signal B.
Claim 2
Dependent Claim
136 words
A lock detector circuit for producing a lock detection signal from output signals I and Q generated by a demodulator of a UQPSK signal, said circuit comprising: first signal processing means for receiving said signals I and Q to produce a signal A at a first terminal: A=KI.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4, where K is a constant value; second signal processing means for receiving said signals I and Q to produce the signal B at a second terminal: B=4(I.sup.2 -Q.sup.2); and a switch having a plurality of switching positions, said switch coupling the control circuits of said demodulator to said first terminal in a first switching position, and coupling the control circuits of said demodulator to said second terminal in a second switching position, whereby said control circuits are responsive to said signal A or signal B.
Claim 3
Dependent Claim
19 words
A lock detector circuit as recited in claim 1, wherein said constant value K is substantially equal to 6.
Claim 4
Dependent Claim
133 words
A lock detector circuit for producing a lock detection signal from output signals I and Q generated by a demodulator of a UQPSK signal, said circuit comprising: first signal processing means for receiving said signals I and Q to produce a signal A at a first terminal: A=KI.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4, where K is a constant value; second signal processing means for receiving said signals I and Q to produce the signal B at a second terminal: B=4(I.sup.2 -Q.sup.2); and a summing circuit coupled to said first terminal and said second terminal for forming the sum of the signals at said first and second terminals, wherein said summing circuit has an output that is coupled to the control circuits of said demodulator, and said control circuits are responsive to said sum of signals.
Claim 5
Dependent Claim
133 words
A lock detector circuit for producing a lock detection signal from output signals I and Q generated by a demodulator of a UQPSK signal, said circuit comprising: first signal processing means for receiving said signals I and Q to produce a signal A at a first terminal: A=KI.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4, where K is a constant value; second signal processing means for receiving said signals I and Q to produce the signal B at a second terminal: B=4(I.sup.2 -Q.sup.2); and a summing circuit coupled to said first terminal and said second terminal for forming the sum of the signals at said first and second terminals, wherein said summing circuit has an output that is coupled to the control circuits of said demodulator, and said control circuits are responsive to said sum of signals.
Claim 6
Dependent Claim
19 words
A lock detector circuit as recited in claim 3, wherein said constant value K is substantially equal to 6.
Claim 7
Dependent Claim
60 words
A lock detector circuit as recited in claim 1, wherein said second signal processing means comprises: first summing means for forming the sum I+Q; second summing means for forming the sum I-Q; and first multiplier means coupled to said first summing means and said second summing means for forming the product 4((I+Q)(I-Q))=B and transmitting said product to said second terminal.
Claim 8
Dependent Claim
99 words
A lock detector circuit as recited in claim 5, wherein said first signal processing means comprises: said second signal processing means; second multiplier means for forming the product 2IQ; third summing means coupled to said second signal processing means and said first multiplier means for forming the sum 2IQ-(I+Q) (I-Q); fourth summing means coupled to said second signal processing means and said first multiplier means for forming the sum 2IQ+(I+Q) (I-Q); and third multiplier means coupled to said third summing means and said fourth summing means for forming the signal A and transmitting said signal to said first terminal.
Claim 9
Independent Claim
94 words
A method for producing a lock detector signal from the output signals I and Q generated by a demodulator of a UQPSK signal, said method comprising the steps of: forming a signal 6I 2 Q 2 -I 4 -Q 4 at a terminal A; forming a signal 4(I 2 -Q 2 ) at a terminal B; determining the ratio of the signals Q/I; and if said ratio is greater than or equal to 0.7, detecting the signal at terminal A; and, if said ratio is less than 0.7, detecting the signal at terminal B.
Claim 10
Independent Claim
94 words
A method for producing a lock detector signal from the output signals I and Q generated by a demodulator of a UQPSK signal, said method comprising the steps of: forming a signal 6I 2 Q 2 -I 4 -Q 4 at a terminal A; forming a signal 4(I 2 -Q 2 ) at a terminal B; determining the ratio of the signals Q/I; and if said ratio is greater than or equal to 0.7, detecting the signal at terminal A; and, if said ratio is less than 0.7, detecting the signal at terminal B.
Claim 11
Independent Claim
75 words
A method for producing a lock detector signal from the output signals I and Q generated by a demodulator of a UQPSK signal, said method comprising the steps of: forming a signal 6I 2 Q 2 -I 4 -Q 4 at a terminal A; forming a signal 4(I 2 -Q 2 ) at a terminal B; and forming the sum of said signals at terminal A and terminal B to produce said lock detector signal.
Claim 12
Independent Claim
75 words
A method for producing a lock detector signal from the output signals I and Q generated by a demodulator of a UQPSK signal, said method comprising the steps of: forming a signal 6I 2 Q 2 -I 4 -Q 4 at a terminal A; forming a signal 4(I 2 -Q 2 ) at a terminal B; and forming the sum of said signals at terminal A and terminal B to produce said lock detector signal.
Claim 13
Dependent Claim
110 words
A method for producing a lock detector signal as recited in claim 7, wherein said step of forming said signal at a terminal A comprises the substeps of: forming the signal at terminal B as recited in claim 7; forming a first product signal 2IQ; forming a first sum signal by adding said first product signal and one-fourth of said signal at terminal B; forming a second sum signal by subtracting one-fourth of said signal at terminal B from said first product signal; and forming a third product signal by multiplying said first sum signal and said second sum signal, and transmitting said third product signal to said terminal A.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-09 | 1995-12-09 | 1996-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-09 | 1999-12-09 | 2000-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-09 | 2003-12-09 | 2004-06-09 | $7700.00 | Window Closed / Lapsed |