US4713630A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BPSK Costas-type PLL circuit having false lock prevention
Assignee: Gilat Satellite Networks Ltd
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Filing: 1986-07-29
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Granted: 1987-12-15
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Expires: 2006-07-29
Abstract
Abstract A BPSK Costas-type PLL circuit in which the circuit is positively prevented from falsely locking on to the input signal and in which the need for a complex lock detector is eliminated. The output levels of both the 0° and 90° sub-loops of the circuit are detected and a difference formed between the detected outputs. When the difference exceeds a predetermined reference level, it is determined that true locking has occurred, whereupon a sweep generator, used in achieving initial lock, is decoupled from the PLL circuit.
Inventors
- 👤 David Matthews
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:18
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/12; H03L2207/00; H03L2207/14; H04L27/0014; H04L2027/0044; H04L2027/0063; H04L2027/0067; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
263 words
A BPSK Costas-type PLL circuit in which false lock-in is prevented by distinguishing between true lock-in and false lock-in, comprising: 0° and 90° sub-loops, said 0° sub-loop comprising a first mixer receiving on a first input a BPSK IF signal, a first low-pass filter and amplifier coupled in series with one another and receiving as an input an output of said first mixer, a multiplier receiving on a first input an output of said first low-pass filter and amplifier, a loop filter having an input coupled to an output of said multiplier, and a voltage-controlled oscillator receiving as a control-voltage input an output of said loop filter, a 0° output of said voltage-controlled oscillator being coupled to a second input of said first mixer, and said 90° sub-loop comprising a second mixer receiving on a first input said BPSK IF signal, a second low-pass filter and amplifier coupled in series with one another and receiving as an input an output of said second mixer, said multiplier receiving on a second input an output of said second low-pass filter and amplifier, said 90° sub-loop including said loop filter and said voltage-controlled oscillator, A 90° output of said voltage-controlled oscillator being coupled to a second input of said second mixer; sweep generator means coupled to said voltage-controlled oscillator for locking said 0° and 90° sub-loops on to said BPSK IF signal; means for detecting a difference in AC signal levels in said 0° and 90° sub-loops; and means for on/off controlling said sweep generator means in response to an output of said difference detecting means.
Claim 2
Dependent Claim
263 words
A BPSK Costas-type PLL circuit in which false lock-in is prevented by distinguishing between true lock-in and false lock-in, comprising: 0° and 90° sub-loops, said 0° sub-loop comprising a first mixer receiving on a first input a BPSK IF signal, a first low-pass filter and amplifier coupled in series with one another and receiving as an input an output of said first mixer, a multiplier receiving on a first input an output of said first low-pass filter and amplifier, a loop filter having an input coupled to an output of said multiplier, and a voltage-controlled oscillator receiving as a control-voltage input an output of said loop filter, a 0° output of said voltage-controlled oscillator being coupled to a second input of said first mixer, and said 90° sub-loop comprising a second mixer receiving on a first input said BPSK IF signal, a second low-pass filter and amplifier coupled in series with one another and receiving as an input an output of said second mixer, said multiplier receiving on a second input an output of said second low-pass filter and amplifier, said 90° sub-loop including said loop filter and said voltage-controlled oscillator, A 90° output of said voltage-controlled oscillator being coupled to a second input of said second mixer; sweep generator means coupled to said voltage-controlled oscillator for locking said 0° and 90° sub-loops on to said BPSK IF signal; means for detecting a difference in AC signal levels in said 0° and 90° sub-loops; and means for on/off controlling said sweep generator means in response to an output of said difference detecting means.
Claim 3
Dependent Claim
39 words
The BPSK Costas-type PLL circuit of claim 1, wherein said on/off controlling means turns off said sweep generator means when said difference is larger than a predetermined level and on when said difference is smaller than said predetermined level.
Claim 4
Dependent Claim
91 words
The BPSK Costas-type PLL circuit of claim 2, wherein said detecting means comprises first and second AC signal level detecting means having inputs coupled to outputs of said 0° and 90° loops, respectively, differential amplifier means receiving on respective differential inputs outputs of said first and second signal level detecting means, means for comparing an output of said differential amplifier means with a reference level, and means for switchably connecting and disconnecting said sweep generator means from said 0° and 90° sub-loops in response to an output of said comparing means.
Claim 5
Dependent Claim
211 words
A BPSK Costas-type PLL circuit comprising: first and second balanced mixers receiving on first inputs thereof an input BPSK signal; first and second low-pass filters having inputs coupled to outputs of said first and second balanced mixers, respectively; first and second amplifiers having inputs coupled to outputs of said first and second low-pass filters, respectively; a multiplier having inputs coupled to outputs of said first and second amplifiers; a loop filter having an input coupled to an output of said multiplier; a voltage-controlled oscillator having a frequency control input coupled to an output of said loop filter and 0° and 90° outputs coupled, respectively, to second inputs of said first and second balanced mixers; a sweep generator; an electronic switch for coupling an output of said sweep generator to said input of said voltage-controlled oscillator; first and second diode detectors having inputs coupled to said outputs of said first and second amplifiers, respectively; a differential amplifier having opposite polarity inputs coupled to outputs of said first and second diode detectors, respectively; means for providing a reference voltage; and a comparator receiving an output of said differential amplifier on a first input and said reference voltage on a second input, an output of said comparator being applied to control said electronic switch.
Claim 6
Dependent Claim
211 words
A BPSK Costas-type PLL circuit comprising: first and second balanced mixers receiving on first inputs thereof an input BPSK signal; first and second low-pass filters having inputs coupled to outputs of said first and second balanced mixers, respectively; first and second amplifiers having inputs coupled to outputs of said first and second low-pass filters, respectively; a multiplier having inputs coupled to outputs of said first and second amplifiers; a loop filter having an input coupled to an output of said multiplier; a voltage-controlled oscillator having a frequency control input coupled to an output of said loop filter and 0° and 90° outputs coupled, respectively, to second inputs of said first and second balanced mixers; a sweep generator; an electronic switch for coupling an output of said sweep generator to said input of said voltage-controlled oscillator; first and second diode detectors having inputs coupled to said outputs of said first and second amplifiers, respectively; a differential amplifier having opposite polarity inputs coupled to outputs of said first and second diode detectors, respectively; means for providing a reference voltage; and a comparator receiving an output of said differential amplifier on a first input and said reference voltage on a second input, an output of said comparator being applied to control said electronic switch.
Claim 7
Dependent Claim
30 words
The BPSK Costas-type PLL circuit of claim 4, wherein a cutoff frequency of said first and second low-pass filters is set to approximately a data rate of said input signal.
Claim 8
Dependent Claim
20 words
The BPSK Costas-type PLL circuit of claim 5, further comprising a limiter disposed between said first amplifier and said multiplier.
Claim 9
Dependent Claim
35 words
The BPSK Costas-type PLL circuit of claim 6, further comprising a third amplifier having an input coupled to said output of said comparator and an output coupled to a control input of said electronic switch.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-14 | 1991-06-15 | 1991-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-14 | 1995-06-15 | 1995-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-14 | 1999-06-15 | 1999-12-15 | $7700.00 | Window Closed / Lapsed |