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US4213096A Expired / Lapsed US ⏱️ 0.0 years remaining

Phaselock receiver with phaselock detector

Assignee: RCA Corp
•
Filing: 1978-04-26
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Granted: 1980-07-15
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Expires: 1998-04-26
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Abstract

Abstract A phaselock loop in a phaselock receiver includes a voltage-controlled oscillator, and a main phase detector receptive to an output of the oscillator and a received signal. Means to detect when the oscillator is phase locked with the received signal includes a quadrature phase detector receptive to a quadrature-phase-shifted oscillation from the oscillator and the received signal. Means are provided to subtract the direct-current component of the output of the main phase detector from the direct-current component of the output of the quadrature phase detector to provide a phaselock-indicating signal which is substantially zero when the oscillator is out-of-lock with the received signal, and which is high when the oscillator is in-lock with the received signal.

Inventors

  • 👤 James W. Daniel, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 04:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/10; H03L7/12; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/26; H03L7/095; Y; Y10; Y10S; Y10S331/00; Y10S331/02

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 105 words
A phaselock receiver including a phaselock detector, comprising a phase lock loop including a voltage-controlled oscillator, and a main phase detector receptive to an output of said oscillator and a received signal, a 90° phase shifter receptive to an output of said oscillator, a quadrature phase detector receptive to a quadraturephase-shifted oscillation from said phase shifter and said received signal, and means to subtract the direct-current component of the output of said main phase detector from the direct-current component of the output of said quadrature phase detector to provide a phaselock-indicating signal which is substantially zero when the oscillator is out-of-lock with the received signal.
Claim 2
Dependent Claim 105 words
A phaselock receiver including a phaselock detector, comprising a phase lock loop including a voltage-controlled oscillator, and a main phase detector receptive to an output of said oscillator and a received signal, a 90° phase shifter receptive to an output of said oscillator, a quadrature phase detector receptive to a quadraturephase-shifted oscillation from said phase shifter and said received signal, and means to subtract the direct-current component of the output of said main phase detector from the direct-current component of the output of said quadrature phase detector to provide a phaselock-indicating signal which is substantially zero when the oscillator is out-of-lock with the received signal.
Claim 3
Dependent Claim 33 words
A phaselock receiver according to claim 1 wherein said means to subtract direct-current components includes a differential amplifier, and low-pass filters coupling outputs of the respective phase detectors to inputs of the amplifier.
Claim 4
Dependent Claim 51 words
A phaselock receiver according to claim 2, and in addition, means to generate a scanning voltage and apply it to said voltage-controlled oscillator to sweep the frequency of the oscillator back and forth, and means responsive to the phaselock-indicating signal from said differential amplifier to stop the scanning voltage from changing.
Claim 5
Dependent Claim 14 words
A phaselock receiver according to claim 3 wherein scanning voltage has a triangular waveform.
Claim 6
Dependent Claim 59 words
A phaselock receiver according to claim 3 wherein said means to generate a scanning voltage includes an oscillator, an up-down counter receptive to the output of said oscillator, means to reverse the up-down counter when it reads a minimum count and when it reads a maximum count, and a digital-to-analog converter receptive to the output of the up-down counter.

References Cited (Backward Citations)

US2833923A Cited
US3311442A Cited
US3160815A Cited
US3290611A Cited
US3768030A Cited
GB1374638A Cited
US4004231A Cited
US3940695A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-07-15 1984-01-14 1984-07-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-07-15 1988-01-14 1988-07-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-07-15 1992-01-14 1992-07-15 $7700.00 Window Closed / Lapsed

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