US5301196A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Half-speed clock recovery and demultiplexer circuit
Assignee: International Business Machines Corp
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Filing: 1992-03-16
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Granted: 1994-04-05
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Expires: 2012-03-16
Abstract
Abstract A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a pair of edge triggered flip-flops using the transitions of the received data as triggers. The outputs of these flip-flops are exclusive OR-ed to provide a signal indicating whether the generated clock leads or lags the received data. The half-speed 1:2 demultiplexer circuit uses the rising and falling edges of a half-speed 90-degree clock to latch the received data through a pair of flip-flops. The outputs of these flip-flops, each triggered by a different edge of the clock, make up two demultiplexed data streams. The clock recovery and demultiplexer circuits of the present invention can be extended to operate at lower clock rates and configured to provide wider demultiplexing.
Inventors
- 👤 John F. Ewen
- 👤 Albert X. Widmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:33
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/085; H03L7/091; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H04L; H04L7/00; H04L7/02; H04L7/033; H04J3/06; H04J3/0635; H04J3/0685
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
175 words
A clock recovery and demultiplexer circuit for recovering a clock signal from a received data signal and for demultiplexing the received data signal, and operating at a fraction of the data rate of the received data signal, said circuit comprising: a. clock signal generating means for generating a reference clock signal having a plurality of phases, said generated reference clock signal having a rate less than the data rate of the received data signal; b. comparing means for comparing the phase angle between said generated reference clock signal and the received data signal; c. frequency adjusting means responsive to said phase angle comparing means for adjusting said rate of said generated reference clock signal to synchronize said generated clock signal and the received data signal; and d. demultiplexing means for demultiplexing the received data signal into parallel signals at data rates lower than the data rate of the received data signal using at least one of each of the phase of said generated reference clock signal and inverted phases of said generated reference clock signal.
Claim 2
Dependent Claim
175 words
A clock recovery and demultiplexer circuit for recovering a clock signal from a received data signal and for demultiplexing the received data signal, and operating at a fraction of the data rate of the received data signal, said circuit comprising: a. clock signal generating means for generating a reference clock signal having a plurality of phases, said generated reference clock signal having a rate less than the data rate of the received data signal; b. comparing means for comparing the phase angle between said generated reference clock signal and the received data signal; c. frequency adjusting means responsive to said phase angle comparing means for adjusting said rate of said generated reference clock signal to synchronize said generated clock signal and the received data signal; and d. demultiplexing means for demultiplexing the received data signal into parallel signals at data rates lower than the data rate of the received data signal using at least one of each of the phase of said generated reference clock signal and inverted phases of said generated reference clock signal.
Claim 3
Dependent Claim
91 words
The clock recovery and demultiplexer circuit of claim 1, wherein: a. said clock signal generating means comprises means for generating 0-degree and 90-degree reference clock signals at one half the data rate of the received data signal; b. said comparing means comprises a phase comparator circuit for comparing the phase angle between said generated reference clock signal and the received data signal; and c. said demultiplexing means comprises means for demultiplexing the received data signal into two separate data streams, both at half the clock rate of the received data signal.
Claim 4
Dependent Claim
46 words
The clock recovery and demultiplexer circuit of claim 2, wherein: said means for generating a 0-degree and 90-degree reference clock signal is a ring oscillator; said half-speed phase comparator circuit comprises two edge-triggered flip-flops and an exclusive OR-gate; and said demultiplexing means comprises two edge-triggered flip-flops.
Claim 5
Dependent Claim
28 words
The clock recovery and demultiplexer circuit of claim 3, further comprising an inverter for inverting the received data signal, and an inverter for inverting said 90-degree clock signal.
Claim 6
Dependent Claim
93 words
The clock recovery and demultiplexer circuit of claim 1, wherein: a. said clock signal generating means comprises means for generating 0-degree, 45-degree, 90-degree and 135-degree reference clock signals at one quarter the data rate of the received data signal; b. said comparing means comprises phase comparator circuit for comparing the phase angle between the generated reference clock signal and the received data signal; and c. said demultiplexing means comprises means for demultiplexing the received data signal into four separate data signals, each at one quarter the clock rate of the received data signal.
Claim 7
Dependent Claim
43 words
The clock recovery and demultiplexer circuit of claim 5, wherein: said means for generating a reference clock signal is a ring oscillator; said quarter speed phase comparator circuit comprises four edge-triggered flip-flops and a parity generator; and said demultiplexing means comprises four flip-flops.
Claim 8
Dependent Claim
30 words
The quarter speed clock recovery and demultiplexer circuit of claim 6 further comprising an inverter for inverting the received data signal, and inverters for inverting the 45-and 135-degree clock signals.
Claim 9
Independent Claim
139 words
A method of recovering a clock signal from a received data signal and for demultiplexing the received data signal, comprising the steps of: a. generating a plurality of phases of a reference clock signal at a rate less than the data rate of the received data signal; b. comparing the phase angle between said generated reference clock signal and the received data stream; c. adjusting the frequency of said generated reference clock signal as a function of said comparing step to thereby synchronize said generated reference clock signal and the received data signal; and d. demultiplexing the received data signal into parallel signals at data rates lower than the data rate of the received data signal, using at lease one each of the phases of the generated reference clock signal and inverted phases of the generated reference clock signal.
Claim 10
Independent Claim
139 words
A method of recovering a clock signal from a received data signal and for demultiplexing the received data signal, comprising the steps of: a. generating a plurality of phases of a reference clock signal at a rate less than the data rate of the received data signal; b. comparing the phase angle between said generated reference clock signal and the received data stream; c. adjusting the frequency of said generated reference clock signal as a function of said comparing step to thereby synchronize said generated reference clock signal and the received data signal; and d. demultiplexing the received data signal into parallel signals at data rates lower than the data rate of the received data signal, using at lease one each of the phases of the generated reference clock signal and inverted phases of the generated reference clock signal.
Claim 11
Dependent Claim
53 words
The method of claim 8 further comprising the steps of: generating a 0-degree and a 90-degree reference clock signal at one half the data rate of the received data signal; and demultiplexing the received data signal into two separate data signals both at one half the clock rate of the received data signal.
Claim 12
Dependent Claim
42 words
The method of claim 8 further comprising the steps of: generating a 0-degree, 45-degree and 90-degree an 135-degree clock signal; and demultiplexing the received data signal into four separate signals each at one quarter the clock rate of the received data signal.
Claim 13
Dependent Claim
176 words
A clock recovery and demultiplexer circuit for recovering clock signal from a received data signal and for demultiplexing the received data stream, and operating at a fraction of the data rate of the received data signal, said circuit comprising: a. an oscillator for generating a reference clock signal having a plurality of phases, said generated reference clock signal having a rate less than the data rate of the received data signal; b. a phase comparator for comparing the phase angle between said generated reference clock signal and the received data signal; c. a feedback loop for adjusting said rate of said generated reference clock signal to synchronize said generated clock signal and the received data stream in response to a lead-lag signal generated by said phase comparator; and a demultiplexer for demultiplexing the received data stream into parallel signals at data rates lower than the data rate of the received data stream using at least one of each of the phase of said generated reference clock signal and inverted phases of said generated reference clock signal.
Claim 14
Dependent Claim
176 words
A clock recovery and demultiplexer circuit for recovering clock signal from a received data signal and for demultiplexing the received data stream, and operating at a fraction of the data rate of the received data signal, said circuit comprising: a. an oscillator for generating a reference clock signal having a plurality of phases, said generated reference clock signal having a rate less than the data rate of the received data signal; b. a phase comparator for comparing the phase angle between said generated reference clock signal and the received data signal; c. a feedback loop for adjusting said rate of said generated reference clock signal to synchronize said generated clock signal and the received data stream in response to a lead-lag signal generated by said phase comparator; and a demultiplexer for demultiplexing the received data stream into parallel signals at data rates lower than the data rate of the received data stream using at least one of each of the phase of said generated reference clock signal and inverted phases of said generated reference clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |