Phase lock loss detector

Claim 5

In a phase locked loop system comprising signal generating means including a voltage-controlled oscillator (VCO) for generating a two level signal S N of frequency f N and having a first duty cycle ratio of high level portion to total cycle period 1/f N , means for generating a two level reference signal S R of frequency f R and having a second duty cycle ratio of high level portion to total cycle period 1/f R different from said first duty cycle ratio, phase detector means responsive to S N and S R for generating a correcting signal E c , said VCO responsive to E c to change its output frequency so that f N =f R and with S N and S R being phase locked with a predetermined phase offset, a phase lock loss detecting circuit comprising: an Exclusive OR (XOR) gate having first and second input terminals and an output terminal for generating an output signal when the signal levels supplied to said input terminals are unequal; means including delay means for supplying S N and S R to said first and second inputs of said XOR gate so that the center points of the high level portions of S N and S R are nominally time aligned with any time difference 2δ 1 in the duty cycle ratios of S N and S R being substantially equally divided between the leading edges and the trailing edges of each half cycle of S N and S R ; AND gate means having first and second input terminals and an output terminal; means responsive to the output signal of said XOR gate to supply said output signal directly to the first input of said AND gate means and to said second input of said AND gate means delayed by a time interval greater than δ 1 ; and means for detecting an output signal from said AND gate means to indicate loss of phase lock.

Claim 6

In a phase locked loop system comprising signal generating means including a voltage-controlled oscillator (VCO) for generating a two level signal S N of frequency f N and having a first duty cycle ratio of high level portion to total cycle period 1/f N , means for generating a two level reference signal S R of frequency f R and having a second duty cycle ratio of high level portion to total cycle period 1/f R different from said first duty cycle ratio, phase detector means responsive to S N and S R for generating a correcting signal E c , said VCO responsive to E c to change its output frequency so that f N =f R and with S N and S R being phase locked with a predetermined phase offset, a phase lock loss detecting circuit comprising: an Exclusive OR (XOR) gate having first and second input terminals and an output terminal for generating an output signal when the signal levels supplied to said input terminals are unequal; means including delay means for supplying S N and S R to said first and second inputs of said XOR gate so that the center points of the high level portions of S N and S R are nominally time aligned with any time difference 2δ 1 in the duty cycle ratios of S N and S R being substantially equally divided between the leading edges and the trailing edges of each half cycle of S N and S R ; AND gate means having first and second input terminals and an output terminal; means responsive to the output signal of said XOR gate to supply said output signal directly to the first input of said AND gate means and to said second input of said AND gate means delayed by a time interval greater than δ 1 ; and means for detecting an output signal from said AND gate means to indicate loss of phase lock.