US4122405A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital logic level signal indication of phase and frequency lock condition in a phase-locked loop
Assignee: National Semiconductor Corp
•
Filing: 1977-10-21
•
Granted: 1978-10-24
•
Expires: 1997-10-21
Abstract
Abstract A digital logic level signal indicates whether a first signal in a phase-locked loop is locked in phase and frequency with a second signal provided to the loop. The digital logic level signal is provided from the sequentially last stage of a counter having a predetermined number of stages. The counter counts cycles in an input signal corresponding to one of the first signal and the second signal. A reset signal pulse having a first predetermined duration is provided to the counter from a pulse width discriminator when the pulse width discriminator detects a phase difference between the first and second signals of greater than a second predetermined duration. The reset signal pulse resets the counter. The digital logic level signal is in a state indicating an in-lock condition when a predetermined number of input signal cycles occur without the counter being reset.
Inventors
- 👤 Gary William Tietz
- 👤 Keith James Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:09
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/26; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L7/089; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
262 words
A system for providing a digital logic level signal that indicates whether a first signal in a phase-locked loop is locked in phase and frequency to a second signal provided to the loop, comprising: a phase comparator coupled to the phase locked loop for providing a first correction signal when the first and second signals are out of phase in one direction, and a second correction signal when the first and second signals are out of phase in the opposite direction; a lock detector coupled to the phase comparator for providing a first digital logic level signal having a first state whenever either the first correction signal or the second correction signal is provided from the phase comparator, and having a second state whenever neither the first correction signal nor the second correction signal is provided from the phase comparator, the second state thereby indicating that the first signal is locked in phase to the second signal; a pulse width discriminator coupled to the lock detector for providing a reset signal pulse having a first predetermined duration when the digital logic level signal from the lock detector is in said first state for at least a second predetermined duration; and a lock discriminator coupled to the pulse width discriminator and responsive to one of the first signal and the second signal as an input signal for providing a second digital logic level signal that indicates that the loop is in lock when a predetermined number of input signal cycles occur without said reset signal pulse being provided by the pulse width discriminator.
Claim 2
Independent Claim
262 words
A system for providing a digital logic level signal that indicates whether a first signal in a phase-locked loop is locked in phase and frequency to a second signal provided to the loop, comprising: a phase comparator coupled to the phase locked loop for providing a first correction signal when the first and second signals are out of phase in one direction, and a second correction signal when the first and second signals are out of phase in the opposite direction; a lock detector coupled to the phase comparator for providing a first digital logic level signal having a first state whenever either the first correction signal or the second correction signal is provided from the phase comparator, and having a second state whenever neither the first correction signal nor the second correction signal is provided from the phase comparator, the second state thereby indicating that the first signal is locked in phase to the second signal; a pulse width discriminator coupled to the lock detector for providing a reset signal pulse having a first predetermined duration when the digital logic level signal from the lock detector is in said first state for at least a second predetermined duration; and a lock discriminator coupled to the pulse width discriminator and responsive to one of the first signal and the second signal as an input signal for providing a second digital logic level signal that indicates that the loop is in lock when a predetermined number of input signal cycles occur without said reset signal pulse being provided by the pulse width discriminator.
Claim 3
Dependent Claim
114 words
A system according to claim 1, wherein the pulse width discriminator comprises: a current source; a Schmitt trigger circuit; an integrator coupled to the input of the Schmitt trigger circuit; and a switch coupled between the current source and the input of the Schmitt trigger circuit and coupled to the lock detector, said switch being responsive to the first digital logic level signal being in its first state for connecting the current source to the input of the Schmitt trigger circuit and the integrator, wherein the integrator causes the Schmitt trigger circuit to provide said reset signal pulse only when current is provided from the current source for at least said second predetermined duration.
Claim 4
Dependent Claim
65 words
A system according to claim 2, wherein the lock discriminator comprises: a counter having a predetermined number of stages corresponding to the predetermined number of input signal cycles to be counted, including a sequentially last stage for providing the second digital logic level signal, wherein each stage is clocked by the input signal and each stage is reset in response to the reset signal pulse.
Claim 5
Dependent Claim
65 words
A system according to claim 1, wherein the lock discriminator comprises: a counter having a predetermined number of stages corresponding to the predetermined number of input signal cycles to be counted, including a sequentially last stage for providing the second digital logic level signal, wherein each stage is clocked by the input signal and each stage is reset in response to the reset signal pulse.
References Cited (Backward Citations)
US3982190A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-23 | 1982-04-24 | 1982-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-23 | 1986-04-24 | 1986-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-23 | 1990-04-24 | 1990-10-24 | $7700.00 | Window Closed / Lapsed |