Phase discriminator

Claim 2

A phase detector for detecting phase synchronism between a first reference input signal and a second input signal comprising: a pulse generator which generates pulses at each transition of the first and second input signals, said pulse generator comprising pulse delaying circuits each which receives the input signals, and first gating means which is coupled to receive the input signals and the outputs from the pulse delaying circuits for producing a high logical output whenever the logical levels of its inputs are not in concert; means coupled to the pulse generator for producing an output determinative of whether the pulses generated occur concurrently; and gating means which compare the first and second input signals to the output of the means for determining concurrence for producing an output indicative of phase relationship, whereby the phase relationship is determined.

Claim 3

The phase detector as recited in claim 1 wherein the pulse delaying circuit comprises: a NAND gate for receiving a signal input into both of its input terminals; a first capacitance coupled to the output of the NAND gate; and a NOR gate which has both of its input terminals coupled to the output of the NAND gate and a first capacitance.

Claim 4

The phase detector as recited in claim 1 wherein the means for determining concurrence comprises: a second gating means coupled to the outputs of the pulse generating means for producing a high logical output when the pulse generating outputs are both at a low logic level; and a third gating means also coupled to the outputs of the outputs of the pulse generating means for producing a high logical output when the pulse outputs are both at a high logical level; a first triggering means connected to the third gating means for producing a high logical pulse after a delay time once it receives a high logical pulse; and a second triggering means connected to the second gating means and the output of the first triggering means for producing a high logic level from the second gating means does not arrive during the period when a high logic level arrives from the second triggering means.

Claim 5

The phase detector as recited in claim 3 wherein the second gating means comprises a NOR gate.

Claim 6

The phase detector as recited in claim 3 wherein the third gating means comprises a NAND and a NOR gate.

Claim 7

The phase detector as recited in claim 3 wherein the first and second triggering means comprise "D" type flip-flops.

Claim 8

The phase detector as recited in claim 6 wherein the second triggering means also comprises a resistor which coupled to the Q and reset terminals of the flip-flop and a capacitor coupled to reset terminal.

Claim 9

The phase detector as recited in claim 3 wherein the gating means for producing an output indicative of phase relationship comprises: a fourth gating means which receives the input signals and produces a logic high when either one is at a logic low and the other one is at a logic high; and a fifth gating means which receives the output from the fourth gating means and the means for determining whether the pulses occur concurrently for providing a high logic level when both these inputs are at a high logic level.

Claim 10

The phase detector as recited in claim 8 wherein one of the input signals is inverted.

Claim 11

The phase detector as recited in claim 1 wherein the pulse generator comprises a pair of flip-flops, one of which is triggerable on the leading edge of the input waveform and the other of which is triggerable on the falling edge of the input waveform.

Claim 12

The phase detector as recited in claim 10 wherein the pulse generator also comprises a gating means coupled to the output of the flip-flops for producing a train of pulses coinciding with each rise and fall of the input pulses.

Claim 13

The phase detector as recited in claim 11 wherein the flip-flops are "D" type flip-flops.

Claim 14

The phase detector as recited in claim 11 wherein the flip-flops also comprise a means for producing pulses of desired width.