US4408165A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital phase detector
Assignee: Alcatel Lucent NV
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Filing: 1981-11-16
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Granted: 1983-10-04
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Expires: 2001-11-16
Abstract
Abstract The invention relates to a digital phase detector for use with a phase-locked loop (PLL) system, to which there is fed a reference signal and a comparison signal and which, in accordance with the phase difference transmits an output signal for controlling a voltage-controlled oscillator (VCO). In conventional types of phase detectors there exists the danger that subsequently to a failure or interruption of the reference signal, the phase detector in certain cases controls the phase difference, following the restarting, not to zero but to 2π. In order to prevent this, the invention proposes the phase detector to be preceded by a correction circuit delaying the switching of the signals to the phase detector, following the restarting of the reference signal, in such a way that the trailing edge of the reference signal is applied to the phase detector either simultaneously with or with a time delay after the trailing edge of the comparison signal. In this way, independently of the phase difference, and subsequently to the restarting of the reference signal, it is safeguarded that the phase difference is controlled to zero.
Inventors
- 👤 Reinhold Braun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:40
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/08; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
254 words
In a digital phase detector having two inputs and two outputs for a phase-locked-loop (PLL) system with a reference signal and a comparison signal, in which the reference signal is capable of being applied to the first input and in which the comparison signal is capable of being applied to the second input, and in which the first output delivers a first output signal whenever the reference signal, in its phase, leads the comparison signal, and the second output delivers a second output signal whenever the reference signal, in its phase, lags behind the comparison signal, with the pulse widths of these output signals each being in proportion to the value of the phase shift between the reference signal and the comparison signal, the improvement comprising that the inputs of said phase detector (PDT) are preceded by a correction circuit (KS) having two inputs and two outputs, with the outputs of said correction circuit (KS) being connected to the inputs of said phase detector (PDT), with both said reference signal (R) and said comparison signal (V) capable of being applied to the inputs of said correction circuit (KS), and that said correction circuit (KS), following an interruption of said reference signal (R), includes means for switching its inputs to its outputs such that the trailing edges of both said reference signal (R) and said comparison signal (V) are switched through simultaneously, or that the trailing edge of said reference signal (R) is switched through subsequently to the trailing edge of said comparison signal (V).
Claim 2
Dependent Claim
254 words
In a digital phase detector having two inputs and two outputs for a phase-locked-loop (PLL) system with a reference signal and a comparison signal, in which the reference signal is capable of being applied to the first input and in which the comparison signal is capable of being applied to the second input, and in which the first output delivers a first output signal whenever the reference signal, in its phase, leads the comparison signal, and the second output delivers a second output signal whenever the reference signal, in its phase, lags behind the comparison signal, with the pulse widths of these output signals each being in proportion to the value of the phase shift between the reference signal and the comparison signal, the improvement comprising that the inputs of said phase detector (PDT) are preceded by a correction circuit (KS) having two inputs and two outputs, with the outputs of said correction circuit (KS) being connected to the inputs of said phase detector (PDT), with both said reference signal (R) and said comparison signal (V) capable of being applied to the inputs of said correction circuit (KS), and that said correction circuit (KS), following an interruption of said reference signal (R), includes means for switching its inputs to its outputs such that the trailing edges of both said reference signal (R) and said comparison signal (V) are switched through simultaneously, or that the trailing edge of said reference signal (R) is switched through subsequently to the trailing edge of said comparison signal (V).
Claim 3
Dependent Claim
99 words
A phase detector as claimed in claim 1, wherein said correction circuit (KS) comprises two switching gates (G1, G2) whose outputs are connected to the outputs of said correction circuit (KS), that each of said switching gates (G1, G2) comprises two inputs of which the one is connected to the associated input of said correction circuit (KS), and of which the other one is capable of being controlled via said switching means which includes a logic circuit performing either the simultaneous or successive switching of said switching gates (G1, G2) subsequently to a failure of said reference signal (R).
Claim 4
Dependent Claim
72 words
A phase detector as claimed in claim 2, wherein said logic circuit comprises a monostable circuit (MF) which is capable of being controlled by the leading edges of said reference signal (R) and remains in the turn-on state (Q=H) as long as said reference signal (R) is applied and which, upon failure of said reference signal (R), upon lapse of the time (ts), initiates the blocking of said switching gates (G1, G2).
Claim 5
Dependent Claim
149 words
A phase detector as claimed in either one of claims 2 or 3, wherein said logic circuit comprises a trigger circuit (G4, G5) which, in the resting state (Q=L) of said monostable circuit (MF), is brought into the resting position (D=H, B=L), that the one output (D) of said trigger circuit (G4, G5), via an inverter (G6) is connected to the second input of said switching gate (G1) as controlled by said reference signal (R), that the other output (B) of said trigger circuit (G4, G5) is connected to the second input of said switching gate (G2) as controlled by said comparison signal (V), and that said trigger circuit (G4, G5), via a gate circuit (G3), which is capable of being controlled by the output signal (Q) of said monostable circuit (MF) and by said comparison signal (V), is capable of being controlled into the operating position (D=L, B=H).
Claim 6
Dependent Claim
44 words
A phase detector as claimed in claim 4, wherein said gate circuit (G3) serves to reset said trigger circuit (G4, G5) to the operating position when said monostable circuit (MF) is in its turned-on state (Q=H) and when said comparison signal (V) is applied.
Claim 7
Dependent Claim
31 words
A phase detector as claimed in claim 4 wherein a capacitor (C) is arranged in parallel with the second input of said switching gate (G1) as controlled by said reference signal.
Claim 8
Dependent Claim
31 words
A phase detector as claimed in claim 5 wherein a capacitor (C) is arranged in parallel with the second input of said switching gate (G1) as controlled by said reference signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-03 | 1987-04-04 | 1987-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-03 | 1991-04-04 | 1991-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-03 | 1995-04-04 | 1995-10-04 | $7700.00 | Window Closed / Lapsed |