US5550878A
Expired / Lapsed
US
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Phase comparator
Assignee: NEC Corp
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Filing: 1994-11-09
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Granted: 1996-08-27
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Expires: 2014-11-09
Abstract
Abstract A phase comparator, a loop filter and a VCO compose a PLL. In the phase comparator, a CMI code defined by a CMI data is synchronized with a VCO clock generated in the VCO and an inverted clock of the VCO clock, respectively, to provide first and second synchronized CMI codes. The first synchronized CMI code is delayed to provide a delayed CMI code by a predetermined time dependent on a period of the VCO clock. The first and second synchronized CMI codes are subject to an exclusive OR logic calculation, thereby generating a phase difference signal. The delayed CMI code and the first synchronized CMI code are subject to an exclusive OR logic calculation, and a result of this exclusive OR logic calculation and the VCO clock are subject to an AND logic calculation to provide an enable signal. Only when the enable signal is high, the phase difference signal is sampled to be used as a phase difference signal in the PLL.
Inventors
- 👤 Seiichiro Shigaki
- 👤 Hiroaki Shimizu
- 👤 Hiroyuki Mizomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:05
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908; H04L25/491; H04L25/4912; H03; H03D; H03D3/00; H03D3/001; H04L7/00; H04L7/02; H04L7/033; H04L7/0054; H04L7/0066; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
167 words
A phase comparator, comprising: means providing phase signal of a coded mark inversion (CMI) code relative to a voltage controlled oscillator (VCO) clock by receiving said CMI code, said VCO clock and a delayed code which is obtained by delaying said CMI code by a predetermined time based on a period of said VCO clock, said CMI code having a row of bits comprising "01", "00" and "11" dependent on CMI data "0" and "1", and said VCO clock having said period for defining a time slot for a bit of said CMI data; means providing an enable signal by receiving said CMI code and said VCO clock, said enable signal being generated at least in two time slots; and means providing a phase difference signal between said CMI code and said VCO clock by receiving said phase signal, when said enable signal is generated, said phase difference signal means having one output line on which a three state signal of said phase difference signal is provided.
Claim 2
Dependent Claim
167 words
A phase comparator, comprising: means providing phase signal of a coded mark inversion (CMI) code relative to a voltage controlled oscillator (VCO) clock by receiving said CMI code, said VCO clock and a delayed code which is obtained by delaying said CMI code by a predetermined time based on a period of said VCO clock, said CMI code having a row of bits comprising "01", "00" and "11" dependent on CMI data "0" and "1", and said VCO clock having said period for defining a time slot for a bit of said CMI data; means providing an enable signal by receiving said CMI code and said VCO clock, said enable signal being generated at least in two time slots; and means providing a phase difference signal between said CMI code and said VCO clock by receiving said phase signal, when said enable signal is generated, said phase difference signal means having one output line on which a three state signal of said phase difference signal is provided.
Claim 3
Dependent Claim
236 words
A phase comparator, comprising: a first flip flop for synchronizing a coded mark inversion (CMI) code with a voltage controlled oscillator (VCO) clock, said CMI code being defined by a CMI data and said VCO clock having a period for defining a time slot for said CMI data; a second flip flop for delaying said CMI code supplied from said first flip flop by a predetermined time determined by said period of said VCO clock; a first exclusive OR circuit for performing exclusive OR logic calculation between outputs of said first and second flip flops; a third flip flop for adjusting a timing of said CMI code by a signal obtained by inverting said VCO clock; a second exclusive OR circuit for performing exclusive OR logic calculation between outputs of said first and third flip flops, said second exclusive OR circuit providing a pulse signal representing a phase difference between said CMI code and said VCO clock; an AND gate for performing AND logic calculation between an output of said first exclusive OR circuit and said VCO clock, said AND gate providing an enable signal having first and second logic states; and an output circuit for outputting said pulse signal supplied from said second exclusive OR circuit by receiving said first logic state of said enable signal, said output circuit having one output line on which a three state signal of said pulse signal is provided.
Claim 4
Dependent Claim
236 words
A phase comparator, comprising: a first flip flop for synchronizing a coded mark inversion (CMI) code with a voltage controlled oscillator (VCO) clock, said CMI code being defined by a CMI data and said VCO clock having a period for defining a time slot for said CMI data; a second flip flop for delaying said CMI code supplied from said first flip flop by a predetermined time determined by said period of said VCO clock; a first exclusive OR circuit for performing exclusive OR logic calculation between outputs of said first and second flip flops; a third flip flop for adjusting a timing of said CMI code by a signal obtained by inverting said VCO clock; a second exclusive OR circuit for performing exclusive OR logic calculation between outputs of said first and third flip flops, said second exclusive OR circuit providing a pulse signal representing a phase difference between said CMI code and said VCO clock; an AND gate for performing AND logic calculation between an output of said first exclusive OR circuit and said VCO clock, said AND gate providing an enable signal having first and second logic states; and an output circuit for outputting said pulse signal supplied from said second exclusive OR circuit by receiving said first logic state of said enable signal, said output circuit having one output line on which a three state signal of said pulse signal is provided.
Claim 5
Dependent Claim
54 words
A phase comparator, according to claim 2, wherein: said output circuit is a three state buffer to represent lead-and lag-phases of said CMI code relative to said VCO clock, when said enable signal is at said first logic state, and a high impedance state, when said enable signal is at said second logic state.
Claim 6
Dependent Claim
20 words
A phase comparator, according to claim 2, wherein: each of said first to third flip flops is a D-flip flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |