Phase/frequency detector for dejitter applications

Claim 2

A phase/frequency detector circuit for use with an oscillator controller to cause the oscillator to generate a controlled signal having a phase and frequency which is closely related to a reference signal, said circuit comprising: a) first means responsive to the reference signal for producing a first intermediate output corresponding to the reference signal; b) second means responsive to the controlled signal for producing a second intermediate output corresponding to the controlled signal; c) third means responsive to said first and second intermediate outputs for producing an oscillator control signal, said third means includes an exclusive NOR (XNOR) having a first input coupled to said first intermediate output and a second input coupled to said second intermediate output; and d) fourth means responsive to a change in frequency of the reference signal, said fourth means coupled to said first and second means, wherein said oscillator control signal has a duty cycle which corresponds to the phase difference between the reference signal and the controlled signal, and a change in the frequency of the reference signal causes the average duty cycle of the oscillator control signal to change.

Claim 3

A circuit according to claim 1 , wherein: said duty cycle is 50% when the reference signal and the controlled signal are phase locked.

Claim 4

A circuit according to claim 1 , wherein: said first means comprises a first D-Q flip-flop having a clock input, a Q output, and a Qb output and a D input which are coupled to each other, said clock input of said first D-Q flip-flop receiving the reference signal and said Q output of said first D-Q flip-flop producing said first intermediate signal, said second means comprises a second D-Q flip-flop having a clock input, a Q output, and a Qb output and a D input which are coupled to each other, where said clock input of said second D-Q flip-flop receives the controlled signal and said Q output of said second D-Q flip-flop produces said second intermediate signal, and said first input of said XNOR gate being coupled to said Q output of said first D-Q flip-flop and said second input of said XNOR gate being coupled to said Q output of said second D-Q flip-flop.

Claim 5

A circuit according to claim 3 , wherein: said fourth means comprises a SET input and a RESET input of said first D-Q flip-flop, a SET input of said second D-Q flip-flop, and an OR gate having two inputs and an output, said output of said OR gate being coupled to said SET input of said second D-Q flip-flop, said two inputs of said OR gate receiving respective indications of increase and decrease in frequency of the reference signal, said SET input of said first D-Q flip-flop receiving indications of increase in frequency of the reference signal and said RESET input of said first D-Q flip-flop receiving indications of decrease in frequency of the reference signal.

Claim 6

A phase/frequency detector for use with a FIFO buffer having overflow and underflow flags, a filter and a voltage controlled oscillator (VCXO) to dejitter a recovered clock signal (RCLK) in a telecommunications node, said circuit comprising: a) first means responsive to the RCLK signal for producing a first intermediate output corresponding to the RCLK signal; b) second means responsive to the VCXO signal for producing a second intermediate output corresponding to the VCXO signal; c) third means responsive to said first and second intermediate outputs for producing an oscillator control signal, said third means includes an exclusive NOR (XNOR) having a first input coupled to said first intermediate output and a second input coupled to said second intermediate output; and d) fourth means responsive to the overflow and underflow flags, said fourth means coupled to said first and second means, wherein said oscillator control signal has a duty cycle which corresponds to the phase difference between the RCLK signal and the VCXO signal, said oscillator control signal being coupled to the filter and the filter being coupled to the VCXO to control the VCXO signal, and an overflow or underflow flag causes the average duty cycle of the oscillator control signal to change.

Claim 7

A phase/frequency detector for use with a FIFO buffer having overflow and underflow flags, a filter and a voltage controlled oscillator (VCXO) to dejitter a recovered clock signal (RCLK) in a telecommunications node, said circuit comprising: a) first means responsive to the RCLK signal for producing a first intermediate output corresponding to the RCLK signal; b) second means responsive to the VCXO signal for producing a second intermediate output corresponding to the VCXO signal; c) third means responsive to said first and second intermediate outputs for producing an oscillator control signal, said third means includes an exclusive NOR (XNOR) having a first input coupled to said first intermediate output and a second input coupled to said second intermediate output; and d) fourth means responsive to the overflow and underflow flags, said fourth means coupled to said first and second means, wherein said oscillator control signal has a duty cycle which corresponds to the phase difference between the RCLK signal and the VCXO signal, said oscillator control signal being coupled to the filter and the filter being coupled to the VCXO to control the VCXO signal, and an overflow or underflow flag causes the average duty cycle of the oscillator control signal to change.

Claim 8

A circuit according to claim 5 , wherein: said duty cycle is 50% when the RCLK signal and the VCXO signal are phase locked.

Claim 9

A circuit according to claim 6 , wherein: said first means comprises a first D-Q flip-flop having a clock input, a Q output, and a Qb output and a D input which are coupled to each other, where said clock input of said first D-Q flip-flop receives the RCLK signal and said Q output of said first D-Q flip-flop produces said first intermediate signal, said second means comprises a second D-Q flip-flop having a clock input, a Q output, and a Qb output and a D input which are coupled to each other, where said clock input of said second D-Q flip-flop receives the VCXO signal and said Q output of said second D-Q flip-flop produces said second intermediate signal, and said first input of said XNOR being coupled to said Q output of said first D-Q flip-flop and said second input of said XNOR being coupled to said Q output of said second D-Q flip-flop.

Claim 10

A circuit according to claim 7 , wherein: said fourth means includes a SET input and a RESET input of said first D-Q flip-flop, a SET input of said second D-Q flip-flop, and an OR gate having two inputs and an output, said output of said OR gate being coupled to said SET input of said second D-Q flip-flop, said two inputs of said OR gate receiving respective overflow and underflow flags, said SET input of said first D-Q flip-flop receiving the overflow flag and said RESET input of said first D-Q flip-flop receiving the underflow flag.

Claim 11

A phase/frequency detector for use with a FIFO buffer having overflow and underflow flags, a filter coupled to a voltage controlled oscillator (VCXO) to dejitter a recovered clock signal (RCLK) in a telecommunications node, said circuit comprising: a) a first flip-flop having a clock input, a D input, a RESET input, a SET input, a Q output, and a Qb output, said clock input of said first flip-flop being coupled to the RCLK signal, said RESET input of said first flip-flop being coupled to the underflow flag, said SET input of said first flip-flop being coupled to the overflow flag, and said Qb output of said first flip-flop being coupled to said D input of said first flip-flop; b) a logical OR means having a first input coupled to the underflow flag, a second input coupled to the overflow flag, and an output; c) a second flip-flop having a clock input, a D input, a SET input, a Q output, and a Qb output, said clock input of said second flip-flop being coupled to the VCXO signal, said SET input of said second flip-flop being coupled to said output of said logical OR means, and said Qb output of said second flip-flop being coupled to said D input of said second flip-flop; and d) a logical XNOR means having a first input coupled to said Q output of said first flip-flop, a second input coupled to said Q output of said second flip-flop, and an output coupled to the filter for controlling the VCXO.

Claim 12

A phase/frequency detector for use with a FIFO buffer having overflow and underflow flags, a filter coupled to a voltage controlled oscillator (VCXO) to dejitter a recovered clock signal (RCLK) in a telecommunications node, said circuit comprising: a) a first flip-flop having a clock input, a D input, a RESET input, a SET input, a Q output, and a Qb output, said clock input of said first flip-flop being coupled to the RCLK signal, said RESET input of said first flip-flop being coupled to the underflow flag, said SET input of said first flip-flop being coupled to the overflow flag, and said Qb output of said first flip-flop being coupled to said D input of said first flip-flop; b) a logical OR means having a first input coupled to the underflow flag, a second input coupled to the overflow flag, and an output; c) a second flip-flop having a clock input, a D input, a SET input, a Q output, and a Qb output, said clock input of said second flip-flop being coupled to the VCXO signal, said SET input of said second flip-flop being coupled to said output of said logical OR means, and said Qb output of said second flip-flop being coupled to said D input of said second flip-flop; and d) a logical XNOR means having a first input coupled to said Q output of said first flip-flop, a second input coupled to said Q output of said second flip-flop, and an output coupled to the filter for controlling the VCXO.

Claim 13

A circuit for dejittering a recovered clock signal (RCLK) in a telecommunications node, said circuit comprising: a) a FIFO buffer for buffering data received at the node, said FIFO buffer having a data input, a data output, a write clock input, a read clock input, an overflow flag, and an underflow flag, said write clock input being coupled to the RCLK signal; b) a voltage controlled oscillator (VCXO) having a control input and an output coupled to said read clock input of said FIFO buffer; c) a filter having an input and an output coupled to said control input of said VCXO; and d) a control circuit including i) a first flip-flop having a clock input, a D input, a RESET input, a SET input, a Q output, and a Qb output, said clock input of said first flip-flop being coupled to the RCLK signal, said RESET input of said first flip-flop being coupled to said underflow flag, said SET input of said first flip-flop being coupled to said overflow flag, and said Qb output of said first flip-flop being coupled to said D input of said first flip-flop, ii) a logical OR means having a first input coupled to said underflow flag, a second input coupled to said overflow flag, and an output, iii) a second flip-flop having a clock input, a D input, a SET input, a Q output, and a Qb output, said clock input of said second flip-flop being coupled to said output of said VCXO, said SET input of said second flip-flop being coupled to said output of said logical OR means, and said Qb output of said second flip-flop being coupled to said D input of said second flip-flop, and iv) a logical XNOR means having a first input coupled to said Q output of said first flip-flop, a second input coupled to said Q output of said second flip-flop, and an output coupled to said input of said filter for controlling the VCXO.

Claim 14

A circuit for dejittering a recovered clock signal (RCLK) in a telecommunications node, said circuit comprising: a) a FIFO buffer for buffering data received at the node, said FIFO buffer having a data input, a data output, a write clock input, a read clock input, an overflow flag, and an underflow flag, said write clock input being coupled to the RCLK signal; b) a voltage controlled oscillator (VCXO) having a control input and an output coupled to said read clock input of said FIFO buffer; c) a filter having an input and an output coupled to said control input of said VCXO; and d) a control circuit including i) a first flip-flop having a clock input, a D input, a RESET input, a SET input, a Q output, and a Qb output, said clock input of said first flip-flop being coupled to the RCLK signal, said RESET input of said first flip-flop being coupled to said underflow flag, said SET input of said first flip-flop being coupled to said overflow flag, and said Qb output of said first flip-flop being coupled to said D input of said first flip-flop, ii) a logical OR means having a first input coupled to said underflow flag, a second input coupled to said overflow flag, and an output, iii) a second flip-flop having a clock input, a D input, a SET input, a Q output, and a Qb output, said clock input of said second flip-flop being coupled to said output of said VCXO, said SET input of said second flip-flop being coupled to said output of said logical OR means, and said Qb output of said second flip-flop being coupled to said D input of said second flip-flop, and iv) a logical XNOR means having a first input coupled to said Q output of said first flip-flop, a second input coupled to said Q output of said second flip-flop, and an output coupled to said input of said filter for controlling the VCXO.