Method for generating digital communication system clock signals & circuitry for performing that method

Claim 3

A method as set forth in claim 1 for phase-locking an output clock to an input signal with input signal transitions between "0" and "1" logic levels, wherein said input signal is an input clock with transitions between "0" and "1" logic levels at said input frequency.

Claim 6

The method for phase-locking an output clock to an input clock set forth in claim 3 included as steps in a method for phase-locking said output clock to a data stream, which method for phase-locking said output clock to a data stream additionally comprises the preliminary steps of: detecting symbol transitions in said data stream; and generating said input clock with its transitions between "0" and "1" logic levels substantially coinciding in time with said symbol transitions.

Claim 9

The method for phase-locking an output clock to an input clock set forth in claim 5 included as steps in a method for phase-locking said output clock to a data stream, which method for phase-locking said output clock to a data stream additionally comprises the preliminary steps of: detecting symbol transitions in said data stream; and generating said input clock with its transitions between "0" and "1" logic levels substantially coinciding in time with said symbol transitions.

Claim 12

The method for phase-locking an output clock to an input clock set forth in claim 7 included as steps in a method for phase-locking said output clock to a data stream, which method for phase-locking said output clock to a data stream additionally comprises the preliminary steps of: detecting symbol transitions in said data stream; and generating said input clock with its transitions between "0" and "1" logic levels substantially coinciding in time with said symbol transitions.

Claim 17

A clock generating circuit for generating an output clock phase-locked with an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a clock generator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks having a frequency (1/m) times said input frequency and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians; a detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; and a phase controller responsive to said phase control signal for simultaneously shifting the phases of said m component clocks ahead or behind so as to reduce any misphasing of the edges of said m component clocks respective to said input signal transitions.

Claim 18

A clock generating circuit for generating an output clock phase-locked with an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a clock generator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks having a frequency (1/m) times said input frequency and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians; a detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; and a phase controller responsive to said phase control signal for simultaneously shifting the phases of said m component clocks ahead or behind so as to reduce any misphasing of the edges of said m component clocks respective to said input signal transitions.

Claim 19

A clock generating circuit as set forth in claim 11, wherein said input signal is an input clock with transitions between "0" and "1" logic levels at said input frequency, and wherein said detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods comprises: a phase detector for comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock to generate said error signal.

Claim 20

A clock generating circuit as set forth in claim 12 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including: a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating an input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

Claim 21

A clock generating circuit as set forth in claim 13, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.

Claim 22

A clock generating circuit as claimed in claim 12, wherein said loop filter comprises: a capacitor for supplying between first and second plates thereof said phase control signal; and a differential transconductance amplifier responding to said error signal supplied from said phase detector for changing the charge stored within said capacitor, charging said capacitor when said error signal is of a first sense of polarity and discharging said capacitor when said error signal is of a second sense of polarity opposite to said first sense of polarity.

Claim 23

A clock generating circuit for generating an output clock phase-locked with an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a clock generator for generating m component clocks of an m-phase output clock, m being an even integer that is twice another integer n greater than one, each of said m component clocks exhibiting respective transitions between "0" and "1" logic levels thereof, having a frequency (1/m) times said input frequency, and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians; a phase detector comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock, for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; and a phase controller responsive to said phase control signal for simultaneously shifting the phases of said m component clocks ahead or behind so as to reduce any misphasing of the edges of said m component clocks respective to said input clock; wherein said phase detector comprises: first and second nodes for supplying said error signal in push/pull; third, fourth and fifth nodes; biasing circuitry tending to pull respective potentials at said first node and at said second node in a first direction and tending to pull potential at said fifth node in a second direction opposite to said first direction; means responsive to said input clock being at "0" logic level for selectively clamping said first node to said third node; means responsive to said input clock being at "0" logic level for selectively clamping said second node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said first node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said second node to said third node; and means for alternately clamping said third node and said fourth node to said fifth node, the alternation of said alternate clamping occurring in response to each change in said logic levels of said m component clocks of said m-phase output clock.

Claim 24

A clock generating circuit for generating an output clock phase-locked with an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a clock generator for generating m component clocks of an m-phase output clock, m being an even integer that is twice another integer n greater than one, each of said m component clocks exhibiting respective transitions between "0" and "1" logic levels thereof, having a frequency (1/m) times said input frequency, and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians; a phase detector comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock, for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; and a phase controller responsive to said phase control signal for simultaneously shifting the phases of said m component clocks ahead or behind so as to reduce any misphasing of the edges of said m component clocks respective to said input clock; wherein said phase detector comprises: first and second nodes for supplying said error signal in push/pull; third, fourth and fifth nodes; biasing circuitry tending to pull respective potentials at said first node and at said second node in a first direction and tending to pull potential at said fifth node in a second direction opposite to said first direction; means responsive to said input clock being at "0" logic level for selectively clamping said first node to said third node; means responsive to said input clock being at "0" logic level for selectively clamping said second node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said first node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said second node to said third node; and means for alternately clamping said third node and said fourth node to said fifth node, the alternation of said alternate clamping occurring in response to each change in said logic levels of said m component clocks of said m-phase output clock.

Claim 25

A clock generating circuit as set forth in claim 16, wherein said means for alternately clamping said third node and said fourth node to said fifth node comprises first through n th means for selectively providing a respective conductive path between said third node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock; and (n+1) th through 2n th means for selectively providing a respective conductive path between said fourth node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock.

Claim 26

A clock generating circuit as set forth in claim 16, wherein said biasing circuitry comprises: a sixth node; a first resistor connecting said first and sixth nodes; a second resistor connecting said second and sixth nodes; and means for causing substantially constant current to circulate through said fifth and sixth nodes.

Claim 27

A clock generating circuit as claimed in claim 16, wherein said loop filter comprises: a capacitor for supplying between first and second plates thereof said phase control signal; and a differential transconductance amplifier responding to said error signal supplied in push/pull from said first and second nodes for changing the charge stored within said capacitor, charging said capacitor when said error signal is of a first sense of polarity and discharging said capacitor when said error signal is of a second sense of polarity opposite to said first sense of polarity.

Claim 28

A clock generating circuit as set forth in claim 16 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including: a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating Uan input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

Claim 29

A clock generating circuit as set forth in claim 20, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.

Claim 30

A clock generating circuit for generating an output clock phase-locked with an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a controlled oscillator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks having a frequency (1/m) times said input frequency and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians, the phase of each of said m component clocks being adjustable responsive to a control signal received by said controlled oscillator; a detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; a loop filter for supplying said control signal in response to said error signal supplied from said phase detector.

Claim 31

A clock generating circuit for generating an output clock phase-locked with an input signal with input signal transitions between "0" and "1" logic levels, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a controlled oscillator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks having a frequency (1/m) times said input frequency and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians, the phase of each of said m component clocks being adjustable responsive to a control signal received by said controlled oscillator; a detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; a loop filter for supplying said control signal in response to said error signal supplied from said phase detector.

Claim 32

A clock generating circuit as set forth in claim 22, wherein said input signal is an input clock with transitions between "0" and "1" logic levels at said input frequency, and wherein said detector for detecting any misphasing of said m component clocks from midpoints of said symbol periods comprises a phase detector for comparing the phasing of said m component clocks respective to said input clock to generate said error signal.

Claim 33

A clock generating circuit as set forth in claim 23 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including: a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating said input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

Claim 34

A clock generating circuit as set forth in claim 24, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.

Claim 35

A clock generating circuit for generating an output clock phase-locked with an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a controlled oscillator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks exhibiting respective transitions between "0" and "1" logic levels thereof, having a frequency (1/m) times said input frequency, and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians, the phase of each of said m component clocks being adjustable responsive to a control signal received by said controlled oscillator; a phase detector comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock, for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; and a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; wherein said phase detector comprises: first and second nodes for supplying said error signal in push/pull; third, fourth and fifth nodes; biasing circuitry tending to pull respective potentials at said first node and at said second node in a first direction and tending to pull potential at said fifth node in a second direction opposite to said first direction; means responsive to said input clock being at "0" logic level for selectively clamping said first node to said third node; means responsive to said input clock being at "0" logic level for selectively clamping said second node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said first node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said second node to said third node; and means for alternately clamping said third node and said fourth node to said fifth node, the alternation of said alternate clamping occurring in response to each change in said logic levels of said m component clocks of said m-phase output clock.

Claim 36

A clock generating circuit for generating an output clock phase-locked with an input clock with transitions between "0" and "1" logic levels at ones of intervals occurring at an input frequency, which said input signal transitions each occur between selected ones of symbol periods that occur consecutively at an input frequency, said clock generating circuit comprising: a controlled oscillator for generating m component clocks of an m-phase output clock, m being an integer greater than one, each of said m component clocks exhibiting respective transitions between "0" and "1" logic levels thereof, having a frequency (1/m) times said input frequency, and having a different respective phase with respect to each other of said component clocks, each of which different respective phases is expressible as a positive multiple less than m of 2π/m radians, the phase of each of said m component clocks being adjustable responsive to a control signal received by said controlled oscillator; a phase detector comparing the phasing of said m component clocks respective to said transitions between "0" and "1" logic levels of said input clock, for detecting any misphasing of said m component clocks from midpoints of said symbol periods to generate an error signal; and a loop filter for supplying a phase control signal in response to said error signal supplied from said phase detector; wherein said phase detector comprises: first and second nodes for supplying said error signal in push/pull; third, fourth and fifth nodes; biasing circuitry tending to pull respective potentials at said first node and at said second node in a first direction and tending to pull potential at said fifth node in a second direction opposite to said first direction; means responsive to said input clock being at "0" logic level for selectively clamping said first node to said third node; means responsive to said input clock being at "0" logic level for selectively clamping said second node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said first node to said fourth node; means responsive to said input clock being at "1" logic level for selectively clamping said second node to said third node; and means for alternately clamping said third node and said fourth node to said fifth node, the alternation of said alternate clamping occurring in response to each change in said logic levels of said m component clocks of said m-phase output clock.

Claim 37

A clock generating circuit as set forth in claim 26, wherein said means for alternately clamping said third node and said fourth node to said fifth node comprises first through n th means for selectively providing a respective conductive path between said third node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock; and (n+1) th through 2n th means for selectively providing a respective conductive path between said fourth node and said fifth node responsive to a respective pair of said m component clocks of said m-phase output clock.

Claim 38

A clock generating circuit as set forth in claim 26, wherein said biasing circuitry comprises: a sixth node; a first resistor connecting said first and sixth nodes; a second resistor connecting said second and sixth nodes; and means for causing substantially constant current to circulate through said fifth and sixth nodes.

Claim 39

A clock generating circuit as claimed in claim 26, wherein said loop filter comprises: a capacitor for supplying between first and second plates thereof said control signal; and a differential transconductance amplifier responding to said error signal supplied in push/pull from said first and second nodes for changing the charge stored within said capacitor, charging said capacitor when said error signal is of a first sense of polarity and discharging said capacitor when said error signal is of a second sense of polarity opposite to said first sense of polarity.

Claim 40

A clock generating circuit as set forth in claim 26 included in a digital communication system for generating a clock phase-locked in quadrature phasing with symbol transitions in an input data stream, said digital communication system also including: a symbol transition detector for detecting symbol transitions occurring between symbol periods in said data stream and generating said input clock with said transitions between "0" and "1" logic levels at said input frequency, which said input clock transitions coincide in time with said symbol transitions.

Claim 41

A clock generating circuit as set forth in claim 30, wherein said m clocks each are of a frequency that is 1/2m times a maximum baud rate of said input data.