Patent US6646322B2 successfully refreshed from Google Patents.
US6646322B2
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US
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Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2001-07-16
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Granted: 2003-11-11
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Expires: 2021-07-16
Abstract
Abstract Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Inventors
- 👤 Eugene A. Fitzgerald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:55
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10D; H10D30/00; H10D30/01; H10D30/051; H10D30/0516; H10D30/60; H10D30/751; H10D30/80; H10D30/801; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8311; H10D84/85; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/3254; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P90/1922; H10W; H10W10/00; H10W10/10; H10W10/181; H10D30/637
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
69 words
A semiconductor structure integrating separate surface channel and buried channel devices, the structure comprising: a. a first strained layer; b. a second strained layer thereunder; c. an intervening spacer layer between and adjacent the first strained layer and the second strained layer; d. a surface-channel device having a carrier channel in the first strained layer; and e. a buried-channel device having a carrier channel in the second strained layer.
Claim 2
Dependent Claim
69 words
A semiconductor structure integrating separate surface channel and buried channel devices, the structure comprising: a. a first strained layer; b. a second strained layer thereunder; c. an intervening spacer layer between and adjacent the first strained layer and the second strained layer; d. a surface-channel device having a carrier channel in the first strained layer; and e. a buried-channel device having a carrier channel in the second strained layer.
Claim 3
Dependent Claim
25 words
The structure of claim 1 , wherein the at least one surface-channel device is a MOSFET comprising a gate dielectric over the first strained layer.
Claim 4
Dependent Claim
30 words
The structure of claim 1 , wherein the at least one buried-channel device is a FET comprising a thinned portion of the first strained layer and a gate dielectric thereover.
Claim 5
Dependent Claim
30 words
The structure of claim 3 , wherein buried-channel device comprises a dopant supply layer in a portion of the spacer layer adjacent the thinned portion of the first strained layer.
Claim 6
Dependent Claim
22 words
The structure of claim 3 , wherein the buried-channel device comprises a dopant supply layer below and adjacent the second strained layer.
Claim 7
Dependent Claim
16 words
The structure of claim 1 , further comprising a platform layer adjacent the second strained layer.
Claim 8
Dependent Claim
16 words
The structure of claim 6 , wherein the platform layer comprises at least one planarized surface.
Claim 9
Dependent Claim
18 words
The structure of claim 1 , wherein the spacer layer is a relaxed composition of silicon and germanium.
Claim 10
Dependent Claim
16 words
The structure of claim 1 , wherein at least one of the strained layers is silicon.
Claim 11
Dependent Claim
14 words
The structure of claim 1 , wherein both of the strained layers are silicon.
Claim 12
Dependent Claim
16 words
The structure of claim 1 , wherein at least the first surface strained layer comprises Ge.
Claim 13
Dependent Claim
15 words
The structure of claim 1 , wherein at least the second strained layer comprises Ge.
Claim 14
Dependent Claim
14 words
The structure of claim 1 , wherein the second strained layer is compressively strained.
Claim 15
Dependent Claim
14 words
The structure of claim 1 , wherein the second strained layer is tensilely strained.
Claim 16
Dependent Claim
21 words
The structure of claim 1 , wherein a carrier channel of a surface-channel device is provided in the second strained layer.
Claim 17
Dependent Claim
15 words
The structure of claim 1 , further comprising a substrate adjacent the second strained layer.
Claim 18
Dependent Claim
15 words
The structure of claim 18 , wherein the substrate comprises at least one planarized surface.
Claim 19
Dependent Claim
19 words
The structure of claim 16 , further comprising an insulator disposed between the substrate and the second strained layer.
Claim 20
Dependent Claim
13 words
The structure of claim 18 , wherein the insulator is SiO 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-11-10 | 2007-05-12 | 2007-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-11-10 | 2011-05-12 | 2011-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-11-10 | 2015-05-12 | 2015-11-11 | $7700.00 | Window Closed / Lapsed |