EP0683522A2
Expired / Lapsed
EP
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CMOS with strained Si/SiGe layers
Assignee: International Business Machines Corp
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Filing: 1995-04-26
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Granted: —
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Expires: 2015-04-26
Abstract
Abstract A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.
Inventors
- 👤 Khaled E. Ismail
- 👤 Frank Stern
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 09:34
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D84/00; H10D84/01; H10D84/02; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
140 words
A semiconductor structure for forming both n and p channel field effect transistors therein comprising: a semiconductor substrate, a plurality of commensurate layers of semiconductor material formed on said substrate, said plurality of layers having compositions selected from the group consisting of silicon, germanium, silicon germanium and alloys thereof, at least a first one of said layers under tensile strain whereby the conduction band is below the Fermi level, at least a second one of said layers under compressive strain whereby the valence band is above the Fermi level, a plurality of n-type regions located at least in said first one of said layers for passing current through said first one of said layers, and a plurality of p-type regions located at least in said second one of said layers for passing current through said second one of said layers.
Claim 2
Dependent Claim
204 words
The semiconductor structure of claim 1, wherein said semiconductor substrate is a single crystalline substrate; a first layer of relaxed Si 1-x Ge x is formed epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, a second layer of n doped Si 1-x Ge x is formed epitaxially on said first layer, a third layer of undoped Si 1-x Ge x is formed epitaxially on said second layer, a fourth layer selected from the group consisting of silicon, germanium, silicon-germanium and alloys thereof is formed epitaxially on said third layer whereby said fourth layer is under tensile strain, a fifth layer of relaxed Si 1-x Ge x is formed epitaxially on said fourth layer, a sixth layer of Si 1-y Ge y is formed epitaxially on said fifth layer where the Ge fraction y is in the range from 0.5 to 1.0 and where y-x > .2 whereby said sixth layer is under compressive strain, a seventh layer of relaxed Si 1-x Ge x is formed epitaxially on said sixth layer, an eighth layer of silicon is formed epitaxially on said seventh layer, and a ninth layer of dielectric material is formed over said eighth layer.
Claim 3
Dependent Claim
28 words
The semiconductor structure of claim 2 further including a tenth layer of polysilicon formed over said ninth layer of dielectric material and patterned lithographically to form gate electrodes.
Claim 4
Dependent Claim
48 words
The semiconductor structure of claim 2 or 3 further including p regions passing from said sixth through eighth layers and n regions passing from said fourth through eighth layers on either side of at least one gate electrode to form a p-channel and a n-channel field effect transistor.
Claim 5
Dependent Claim
33 words
The semiconductor structure of any of the preceding claims 2 to 4 further including p-type and n-type source and drain regions located at least in said second layer or in said fourth layer.
Claim 6
Dependent Claim
35 words
The semiconductor structure of any of the preceding claims 3 to 5 further including means for interconnecting said gate electrodes, said p regions and said n regions to form complementary metal oxide semiconductor (CMOS) logic.
Claim 7
Dependent Claim
45 words
The semiconductur structure of any of the preceding claims 2 to 6 wherein said first layer further includes p type regions and n type regions below the area of n channel or p channel transistors to prevent parasitic currents in or below said first layer.
Claim 8
Dependent Claim
175 words
A field effect transistor having a source region, drain region and increased electron mobility in its channel comprising: a semiconductor substrate, a first layer of relaxed Si 1-x Ge x formed epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, a second layer of n doped Si 1-x Ge x formed epitaxially on said first layer, a third layer of undoped Si 1-x Ge x formed epitaxially on said second layer, a fourth layer selected from the group consisting of silicon, germanium, silicon-germanium and alloys thereof formed epitaxially on said third layer whereby said fourth layer is under tensile strain whereby the conduction band is split into a 2-fold and a 4-fold degenerate band with electron mobility in the 2-fold band being in the range from 2,000 to 2,500 cm ²/Vs at 300K, said source region and said drain region located at least in said fourth layer, a fifth layer of dielectric material formed over said fourth layer, and a gate electrode formed over said fifth layer.
Claim 9
Dependent Claim
169 words
A field effect transistor having a source region, drain region and increased hole mobility ill its channel comprising: a semiconductor substrate, a first layer of relaxed Si 1-x Ge x formed epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, a second layer of Si 1-y Ge y formed epitaxially on said first layer where the Ge fraction y is in the range from 0.5 to 1 and where y-x > 0.2 whereby said second layer is under compressive strain resulting in hole confinement therein, said source region and said drain region located at least in said second layer, a third layer of silicon formed epitaxially on said second layer, a fourth layer of dielectric material formed over said third layer, a gate electrode formed over said fourth layer and a fifth layer of Si 1-z Ge z formed epitaxially between said second layer and said third layer where the Ge fraction z is in the range from 0.20 to 0.5.
Claim 10
Independent Claim
168 words
A method for forming a semiconductor structure for for forming both n and p channel field effect transistors therein comprising the steps of: selecting a semiconductor substrate, forming a plurality of commensurate layers of semiconductor material on said substrate, said plurality of layers having compositions selected from the group consisting of silicon, germanium, silicon germanium and alloys thereof, said step of forming a plurality of commensurate layers further includes the steps of forming at least a first one of said layers under tensile strain whereby the conduction band is below the Fermi level and forming at least a second one of said layers under compressive strain whereby the valence band is above the Fermi level, forming a plurality of n-type regions located at least in said first one of said layers for passing current through said first one of said layers, and forming a plurality of p-type regions located at least in said second one of said layers for passing current through said second one of said layers.
Claim 11
Dependent Claim
194 words
The method of claim 10 comprising the steps of: selecting a single crystalline substrate, forming a first layer of relaxed Si 1-x Ge x epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, forming a second layer of n doped Si 1-x Ge x epitaxially on said first layer, forming a third layer of undoped Si 1-x Ge x epitaxially on said second layer, forming a fourth layer selected from the group consisting of silicon, germanium, silicon-germanium and alloys thereof epitaxially on said third layer whereby said fourth layer is under tensile strain, forming a fifth layer of relaxed Si 1-x Ge x epitaxially on said fourth layer, forming a sixth layer of Si 1-y Ge y epitaxially on said fifth layer where the Ge fraction y is in the range from 0.5 to 1.0 and where y-x > .2 whereby said sixth layer is under compressive strain, forming a seventh layer of relaxed Si 1-x Ge x epitaxially on said sixth layer, forming an eighth layer of silicon epitaxially on said seventh layer, and forming a ninth layer of dielectric material over said eighth layer.
Claim 12
Dependent Claim
33 words
The method of claim 11 further including the step of forming a tenth layer of polysilicon over said ninth layer of dielectric material and patterning lithographically said tenth layer to form gate electrodes.
Claim 13
Dependent Claim
50 words
The method of claim 11 or 12 further including the step of forming p regions passing from said sixth through eighth layers and n regions passing from said fourth through eighth layers on either side of at least one gate electrode to form a p-channel and n-channel field effect transistor.
Claim 14
Independent Claim
36 words
The method of any of the preceding claims 11 to 13 further including the step of forming p-type and n-type source and drain regions located at least in said second layer or in said fourth layer.
Claim 15
Independent Claim
35 words
The method of any of the preceding claims 12 to 14 further including the step of interconnecting said gate electrodes, said p regions and said n regions to form complementary metal oxide semiconductor (CMOS) logic.
Claim 16
Independent Claim
183 words
A method for forming a field effect transistor having a source region, drain region and increased electron mobility in its channel comprising the steps of: selecting a semiconductor substrate, forming a first layer of relaxed Si 1-x Ge x epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, forming a second layer of n doped Si 1-x Ge x epitaxially on said first layer, forming a third layer of undoped Si 1-x Ge x epitaxially on said second layer, forming a fourth layer selected from the group consisting of silicon, germanium, silicon-germanium and alloys thereof epitaxially on said third layer whereby said fourth layer is under tensile strain whereby the conduction band is split into a 2-fold and a 4-fold degenerate band with electron mobility in the 2-fold band being in the range from 2,000 to 2,500 cm ²/Vs at 300K, forming said source region and said drain region in at least said fourth layer, forming a fifth layer of dielectric material over said fourth layer, and forming a gate electrode over said fifth layer.
Claim 17
Independent Claim
177 words
A method for forming a field effect transistor having a source region, drain region and increased hole mobility in its channel comprising the steps of: selecting a semiconductor substrate, forming a first layer of relaxed Si 1-x Ge x epitaxially on said substrate where the Ge fraction x is in the range from 0.20 to 0.5, forming a second layer of Si 1-y Ge y epitaxially on said first layer where the Ge fraction y is in the range from 0.5 to 1 and where y-x > 0.2 whereby said second layer is under compressive strain resulting in hole confinement therein, forming said source region and said drain region in at least said second layer, forming a third layer of silicon epitaxially on said second layer, forming a fourth layer of dielectric material over said third layer, forming a gate electrode over said fourth layer and forming a fifth layer of Si 1-z Ge z epitaxially between said second layer and said third layer where the Ge fraction z is in the range from 0.20 to 0.5.
References Cited (Backward Citations)
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