US6593641B1
Expired / Lapsed
US
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Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 2001-07-16
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Granted: 2003-07-15
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Expires: 2021-07-16
Abstract
Abstract Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Inventors
- 👤 Eugene A. Fitzergald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/801; H10D30/01; H10D30/051; H10D30/0516; H10D30/60; H10D30/751; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/3242; H10P14/3244; H10P14/3254; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P90/1922; H10W; H10W10/00; H10W10/10; H10W10/181; H10D30/637; H10D84/8311
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
15 words
A SiGe heterostructure on a relaxed SiGe layer comprising active device layers and sacrificial layers.
Claim 2
Dependent Claim
15 words
A SiGe heterostructure on a relaxed SiGe layer comprising active device layers and sacrificial layers.
Claim 3
Dependent Claim
17 words
The structure of claim 1 , wherein the sacrificial layers comprise SiO 2 and semiconductor surface layers.
Claim 4
Dependent Claim
19 words
The structure of claim 2 , wherein the semiconductor surface layers comprise at least one layer of polycrystalline Si.
Claim 5
Dependent Claim
19 words
The structure of claim 2 , wherein the semiconductor surface layers comprise at least one layer of polycrystalline SiGe.
Claim 6
Dependent Claim
19 words
The structure of claim 2 , wherein the semiconductor surface layers comprise at least one layer of polycrystalline Ge.
Claim 7
Dependent Claim
19 words
The structure of claim 2 , wherein the semiconductor surface layers comprise at least one layer of amorphous Si.
Claim 8
Dependent Claim
19 words
The structure of claim 2 , wherein the semiconductor surface layers comprise at least one layer of amorphous Ge.
Claim 9
Dependent Claim
19 words
The structure of claim 2 , wherein the semiconductor surface layers comprise at least one layer of amorphous SiGe.
Claim 10
Dependent Claim
26 words
A SiGe heterostructure comprising a layer of SiGe having an average surface roughness less than 2 nm, regrown device layers thereover, and regions including alloyed metal-Si—Ge.
Claim 11
Dependent Claim
26 words
A SiGe heterostructure comprising a layer of SiGe having an average surface roughness less than 2 nm, regrown device layers thereover, and regions including alloyed metal-Si—Ge.
Claim 12
Dependent Claim
11 words
The structure of claim 9 , wherein the metal comprises Ti.
Claim 13
Dependent Claim
11 words
The structure of claim 9 , wherein the metal comprises Co.
Claim 14
Dependent Claim
11 words
The structure of claim 9 , wherein the metal comprises Ni.
Claim 15
Dependent Claim
92 words
A SiGe FET comprising: (i) a gate region comprising a relaxed SiGe layer, at least one SiGe device layer, a surface Si layer, and gate stack layers; and (ii) source and drain contact areas adjacent to but differing in structure from the gate regions, the source and drain contact areas comprising a first relaxed SiGe layer having a first Ge concentration, SiGe device layers, a Si layer, a second SiGe layer having a second Ge concentration higher than the first Ge concentration, and, thereover, a surface Si layer alloy with a metal.
Claim 16
Dependent Claim
92 words
A SiGe FET comprising: (i) a gate region comprising a relaxed SiGe layer, at least one SiGe device layer, a surface Si layer, and gate stack layers; and (ii) source and drain contact areas adjacent to but differing in structure from the gate regions, the source and drain contact areas comprising a first relaxed SiGe layer having a first Ge concentration, SiGe device layers, a Si layer, a second SiGe layer having a second Ge concentration higher than the first Ge concentration, and, thereover, a surface Si layer alloy with a metal.
Claim 17
Dependent Claim
11 words
The FET of claim 13 , wherein the metal comprises Ti.
Claim 18
Dependent Claim
11 words
The FET of claim 13 , wherein the metal comprises Co.
Claim 19
Dependent Claim
11 words
The FET of claim 13 , wherein the metal comprises Ni.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-07-14 | 2007-01-13 | 2007-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-07-14 | 2011-01-13 | 2011-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-07-14 | 2015-01-13 | 2015-07-15 | $7700.00 | Window Closed / Lapsed |