US6107653A
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Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
Assignee: Massachusetts Institute of Technology
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Filing: 1998-06-23
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Granted: 2000-08-22
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Expires: 2018-06-23
Abstract
Abstract A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer oil the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.
Inventors
- 👤 Eugene A. Fitzgerald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:42
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/32; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/3248; H10P14/3254; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; Y; Y10; Y10S; Y10S438/00; Y10S438/933
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
64 words
A semiconductor structure comprising: a semiconductor substate; at least one first crystalline epitaxial layer on said substrate, said first layer having a surface which is plananzed in order to smooth said surface; and at least one second crystalline epitaxial layer on said at least one first layer, wherein said at least one first crystalline epitaxial layer is lattice mismatched with respect to said substrate.
Claim 2
Dependent Claim
64 words
A semiconductor structure comprising: a semiconductor substate; at least one first crystalline epitaxial layer on said substrate, said first layer having a surface which is plananzed in order to smooth said surface; and at least one second crystalline epitaxial layer on said at least one first layer, wherein said at least one first crystalline epitaxial layer is lattice mismatched with respect to said substrate.
Claim 3
Dependent Claim
26 words
The structure of claim 1, wherein said at least one second crystalline epitaxial layer is lattice mismatched with respect to said at least one first layer.
Claim 4
Dependent Claim
19 words
The structure of claims 2, wherein said at least one second layer comprises a composition graded relaxed epitaxial region.
Claim 5
Dependent Claim
19 words
The structure of claims 1, wherein said at least one first layer comprises a composition graded relaxed epitaxial region.
Claim 6
Dependent Claim
24 words
The structure of claim 1, wherein subsequent epitaxial layers are provided on said second layer, each of which comprises a surface which is planarized.
Claim 7
Dependent Claim
14 words
The structure of claim 1, wherein said first layer is planarized by chemical-mechanical polishing.
Claim 8
Dependent Claim
60 words
The structure of claim 1, wherein said at least one first or said at least one second layers comprise alloys of Ge x Si 1-x from x=0 to about x≈35% are grown at 750° C., alloys from x=35 to about x≈75% are grown at between 650° C. and 750° C., and alloys greater than 75% are grown at 550° C.
Claim 9
Dependent Claim
70 words
A semiconductor structure comprising: a semiconductor substrate; at least one first crystalline epitaxial layer on said substrate, said first layer having a surface which is planarized in order to smooth said surface; and at least one second crystalline epitaxial layer on said at least one first layer, wherein said first and second crystalline epitaxial layers are lattice mismatched with respect to said substrate and said first crystalline epitaxial layer, respectively.
Claim 10
Dependent Claim
70 words
A semiconductor structure comprising: a semiconductor substrate; at least one first crystalline epitaxial layer on said substrate, said first layer having a surface which is planarized in order to smooth said surface; and at least one second crystalline epitaxial layer on said at least one first layer, wherein said first and second crystalline epitaxial layers are lattice mismatched with respect to said substrate and said first crystalline epitaxial layer, respectively.
Claim 11
Dependent Claim
17 words
The structure of claims 8, wherein said first and second layers comprise composition graded relaxed epitaxial regions.
Claim 12
Dependent Claim
26 words
The structure of claim 9, wherein said at least one first layer comprises a first composition graded relaxed epitaxial region and a first uniform composition layer.
Claim 13
Dependent Claim
26 words
The structure of claim 10, wherein said at least one second layer comprises a second uniform composition layer and a second composition graded relaxed epitaxial region.
Claim 14
Dependent Claim
22 words
The structure of claim 11, wherein said first and second uniform composition layers are substantially lattice mismatched with respect to each other.
Claim 15
Dependent Claim
32 words
The structure of claim 11, wherein the surface of said at least one second layer comprises substantially fewer threading dislocations and dislocation pile-ups than would occur without planarization of said first layer.
Claim 16
Dependent Claim
35 words
The structure of claim 11, wherein said substrate comprises silicon, and said first and second composition graded relaxed epitaxial regions and said first and second uniform composition layers comprise a Ge x Si 1-x alloy.
Claim 17
Dependent Claim
15 words
The structure of claim 14, wherein the planarization occurs at a composition of approximately 50%.
Claim 18
Dependent Claim
16 words
The structure of claim 15, wherein the final Ge concentration is approximately between 70 and 100%.
Claim 19
Dependent Claim
25 words
The structure of claim 14, wherein compressive strain is incorporated in said graded region to offset the tensile strain that is incorporated during thermal processing.
Claim 20
Dependent Claim
105 words
A semiconductor structure comprising: a semiconductor substrate; at least one first crystalline epitaxial layer on said substrate, said first layer having a surface which is planarized in order to smooth said surface; and at least one second crystalline epitaxial layer on said at least one first layer, wherein said at least one second crystalline epitaxial layer comprises a surface which is planarized, and wherein a first planarization occurs at approximately between Ge 0 .20 Si 0 .80 and Ge 0 .35 Si 0 .65, and a second planarization occurs at approximately between Ge 0 .50 Si 0 .50 and Ge 0 .70 Si 0 .30.
Claim 21
Dependent Claim
105 words
A semiconductor structure comprising: a semiconductor substrate; at least one first crystalline epitaxial layer on said substrate, said first layer having a surface which is planarized in order to smooth said surface; and at least one second crystalline epitaxial layer on said at least one first layer, wherein said at least one second crystalline epitaxial layer comprises a surface which is planarized, and wherein a first planarization occurs at approximately between Ge 0 .20 Si 0 .80 and Ge 0 .35 Si 0 .65, and a second planarization occurs at approximately between Ge 0 .50 Si 0 .50 and Ge 0 .70 Si 0 .30.
References Cited (Backward Citations)
US5298452A
Cited
US5177583A
Cited
EP0514018A2
Cited
US5442205A
Cited
US5659187A
Cited
FR2701599A1
Cited
US5399522A
Cited
US5534713A
Cited
US5630905A
Cited
US5714777A
Cited
US5891769A
Cited
US5906951A
Cited
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