US6590427B2 — Phase frequency detector circuit having reduced d…

Claim 1

Independent Claim 132 words

A phase detector for detecting a phase difference between an incoming data signal and a fed-back clock signal and for generating a plurality output signals to a charge pump to control the charge pump, the phase detector comprising: an edge detector for detecting an edge of the data signal and the fed-back clock signal and producing at least one control signal; and a latch that receives the at least one control signal and generates the plurality of output signals responsive to the at least one control signal, wherein a combination of the output signals is indicative of the phase difference between the data signal and the fed-back clock signal, and wherein the output signals have substantially equal duty cycles when the data signal and the fed-back clock signal are substantially in phase.

Claim 2

Dependent Claim 132 words

A phase detector for detecting a phase difference between an incoming data signal and a fed-back clock signal and for generating a plurality output signals to a charge pump to control the charge pump, the phase detector comprising: an edge detector for detecting an edge of the data signal and the fed-back clock signal and producing at least one control signal; and a latch that receives the at least one control signal and generates the plurality of output signals responsive to the at least one control signal, wherein a combination of the output signals is indicative of the phase difference between the data signal and the fed-back clock signal, and wherein the output signals have substantially equal duty cycles when the data signal and the fed-back clock signal are substantially in phase.

Claim 3

Dependent Claim 24 words

A phase detector as defined in claim 1 wherein the combination of the output signals is an integration function performed by a charge pump.

Claim 4

Dependent Claim 80 words

A phase detector as defined in claim 1 wherein a first one of the output signals is high for approximately half a duty cycle plus an amount of time related to the difference in phase between the data signal and the fed-back clock signal, and a second one of the output signals is high for approximately half a duty cycle minus an amount of time related to the difference in phase between the data signal and the fed-back clock signal.

Claim 5

Dependent Claim 60 words

A phase detector as defined in claim 3 wherein duty cycles for the output control signals approximates a 50/50 duty cycle when the data signal and the fed-back clock signal are substantially in phase, wherein a 50/50 duty cycle relates to each pulse having a width that is substantially equal to half the time between rising edges of each pulse.

Claim 6

Dependent Claim 18 words

A phase detector as defined in claim 1 wherein the phase detector further comprises a missing pulse detector.

Claim 7

Dependent Claim 34 words

A phase detector as defined in claim 5 wherein the edge detector comprises a plurality of flip flops and wherein the latch comprises at least two NAND gates configured to form a set/reset latch.

Claim 8

Dependent Claim 30 words

A phase detector as defined in claim 5 wherein the missing pulse detector comprises a flip flop and which effectively disables the phase detector when a missing pulse is detected.

Claim 9

Dependent Claim 23 words

A phase detector as defined in claim 5 used in combination with a voltage controlled oscillator to generate a phase lock loop system.

Claim 10

Independent Claim 112 words

A method of generating an output clock signal based on an input data signal, the method comprising: a) detecting a phase difference between the input data signal and a fed-back clock signal; b) conducting at least two control signals representative of the phase difference to a charge pump, wherein the control signals are digital pulse signals having substantially equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase; c) generating a voltage signal in response to the at least two control signals; and d) conducting the voltage signal to a voltage-controlled oscillator, which produces an oscillating output clock signal based on the voltage signal received.

Claim 11

Independent Claim 112 words

A method of generating an output clock signal based on an input data signal, the method comprising: a) detecting a phase difference between the input data signal and a fed-back clock signal; b) conducting at least two control signals representative of the phase difference to a charge pump, wherein the control signals are digital pulse signals having substantially equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase; c) generating a voltage signal in response to the at least two control signals; and d) conducting the voltage signal to a voltage-controlled oscillator, which produces an oscillating output clock signal based on the voltage signal received.

Claim 12

Dependent Claim 51 words

A method as defined in claim 9 wherein the act of generating a voltage signal (c) is performed by the charge pump that integrates the at least two control signals, and wherein the voltage signal is minimal when the input data signal and the fed-back clock signal are substantially in phase.

Claim 13

Dependent Claim 42 words

A method as defined in claim 10 further comprising: e) detecting a missing pulse in the data signal; and f) modifying the at least two control signals in response to detecting the missing pulse to reduce the effect on the charge pump.

Claim 14

Dependent Claim 36 words

A method as define in claim 11 wherein the act of modifying the at least two control signals (f) further comprises reversing the values of the at least two control signals upon detecting the missing pulse.

Claim 15

Dependent Claim 99 words

A phase lock loop for generating an output clock signal having substantially the same phase as an input data signal, the phase lock loop having a charge pump and a voltage controlled oscillator, the phase lock loop comprising: a digital phase detector for detecting the phase difference between the input data signal and a fed-back clock signal; and means for conducting two control signals to the charge pump in response to detecting the phase difference, wherein the two control signals have substantially equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase.

Claim 16

Dependent Claim 99 words

A phase lock loop for generating an output clock signal having substantially the same phase as an input data signal, the phase lock loop having a charge pump and a voltage controlled oscillator, the phase lock loop comprising: a digital phase detector for detecting the phase difference between the input data signal and a fed-back clock signal; and means for conducting two control signals to the charge pump in response to detecting the phase difference, wherein the two control signals have substantially equal duty cycles when the input data signal and the fed-back clock signal are substantially in phase.

Claim 17

Dependent Claim 25 words

A phase lock loop for generating an output clock as defined in claim 13 wherein the system further comprises means for detecting a missing pulse.

Claim 18

Dependent Claim 38 words

A phase lock loop system as defined in claim 13 wherein the duty cycles of the control signals are approximate a 50/50 duty cycle when the input data signal and the fed-back clock signal are substantially in phase.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-07-07	2007-01-06	2007-07-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-07-07	2011-01-06	2011-07-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-07-07	2015-01-06	2015-07-08	$7700.00	Window Closed / Lapsed

Phase frequency detector circuit having reduced dead band

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