Phase detector and timing extracting circuit using phase detector

Claim 2

A phase detector for detecting the phase difference between a data signal and a clock signal, said phase detector comprising: an edge detector for detecting a rising edge and a falling edge of said data signal and outputting an edge signal; and a D flip flop (D-FF) which is provided with a CLOCK input terminal to which a first signal is input, a DATA input terminal to which a second signal is input and an output terminal for outputting a stored logical value, and which stores and outputs the logical value of said second signal in the instant of a rising edge of said first signal and holds said logical signal until the rising edge of the next first signal; wherein said edge signal is input to said CLOCK input terminal of said D-FF as said first signal; said clock signal is input to said DATA input terminal of said D-FF as said second signal; and a signal corresponding to said phase difference between said data signal and said clock signal is taken out of said output terminal of said D-FF.

Claim 3

A phase detector according to claim 1, wherein said edge detector includes a delay circuit for delaying said data signal by a predetermined time, and a multiplier for multiplying said data signal and the output signal of said delay circuit so as to generate the edge signal which rises at the rising edge and the falling edge of said data signal.

Claim 4

A phase detector according to claim 1, wherein said edge detector includes a delay circuit for delaying said data signal by a predetermined time, and an EXOR circuit for executing an exclusive OR of said data signal and the output signal of said delay circuit so as to generate the edge signal which rises at the rising edge and the falling edge of said data signal.

Claim 5

A phase detector according to claim 1, wherein said edge detector includes a delay circuit for delaying said data signal by a predetermined time, and a mixer for mixing and multiplying said data signal and the output signal of said delay circuit so as to generate the edge signal which rises at the rising edge and the falling edge of said data signal.

Claim 6

A phase detector according to claim 1, wherein said edge detector includes a differentiator for differentiating said data signal, and a full-wave rectifier for generating the edge signal which rises at the rising edge and the falling edge of said data signal by the full-wave rectification of the output signal of said differentiator.

Claim 7

A phase detector according to claim 5, wherein said differentiator is constituted by a stub.

Claim 8

A timing extracting circuit for generating a clock signal which indicates the timing for discriminating a data signal and controlling the phase of the clock signal so that the phase relationship between the clock signal and the data signal is optimal, said timing extracting circuit comprising: a phase detector for detecting phase difference between a data signal and a clock signal; and a clock signal generator for generating the clock signal so that said phase difference is optimal; wherein said phase detector has an edge detector for detecting a rising edge and a falling edge of said data signal and outputting an edge signal, and a D flip flop (D-FF) which is provided with a CLOCK input terminal to which a first signal is input, a DATA input terminal to which a second signal is input and an output terminal for outputting a stored logical value, and which stores and outputs said logical value of said second signal in the instant of a rising edge of said first signal and holds said logical signal until the rising edge of the next first signal; said edge signal is input to said CLOCK input terminal of said D-FF as said first signal; said clock signal is input to said DATA input terminal of said D-FF as said second signal; and a signal corresponding to said phase difference between said data signal and said clock signal is taken out of said output terminal of said D-FF.

Claim 9

A timing extracting circuit for generating a clock signal which indicates the timing for discriminating a data signal and controlling the phase of the clock signal so that the phase relationship between the clock signal and the data signal is optimal, said timing extracting circuit comprising: a phase detector for detecting phase difference between a data signal and a clock signal; and a clock signal generator for generating the clock signal so that said phase difference is optimal; wherein said phase detector has an edge detector for detecting a rising edge and a falling edge of said data signal and outputting an edge signal, and a D flip flop (D-FF) which is provided with a CLOCK input terminal to which a first signal is input, a DATA input terminal to which a second signal is input and an output terminal for outputting a stored logical value, and which stores and outputs said logical value of said second signal in the instant of a rising edge of said first signal and holds said logical signal until the rising edge of the next first signal; said edge signal is input to said CLOCK input terminal of said D-FF as said first signal; said clock signal is input to said DATA input terminal of said D-FF as said second signal; and a signal corresponding to said phase difference between said data signal and said clock signal is taken out of said output terminal of said D-FF.

Claim 10

A timing extracting circuit according to claim 7, wherein said edge detector includes a delay circuit for delaying said data signal by a predetermined time, and a multiplier for multiplying said data signal and the output signal of said delay circuit so as to generate the edge signal which rises at the rising edge and the falling edge of said data signal.

Claim 11

A timing extracting circuit according to claim 7, wherein said edge detector includes a delay circuit for delaying said data signal by a predetermined time, and an EXOR circuit for executing an exclusive OR of said data signal and the output signal of said delay circuit so as to generate the edge signal which rises at the rising edge and the falling edge of said data signal.

Claim 12

A timing extracting circuit according to claim 7, wherein said edge detector includes a delay circuit for delaying said data signal by a predetermined time, and a mixer for mixing and multiplying said data signal and the output signal of said delay circuit so as to generate the edge signal which rises at the rising edge and the falling edge of said data signal.

Claim 13

A timing extracting circuit according to claim 7, wherein said edge detector includes a differentiator for differentiating said data signal, and a full-wave rectifier for generating the edge signal which rises at the rising edge and the falling edge of said data signal by the full-wave rectification of the output signal of said differentiator.

Claim 14

A timing extracting circuit according to claim 11, wherein said differentiator is constituted by a stub.