Bit synchronizer for decoding data

Claim 2

Apparatus for producing a clock signal for use in decoding a Miller-encoded data signal, comprising: means for providing an output pulse of a predetermined duration at each transition of the Miller-encoded data signal; voltage-controlled oscillator means for producing the clock signal; processor means responsive to the clock signal and said output pulses for producing a first synchronizing signal at a first output terminal, wherein said first synchronizing signal is a plurality of pulses when the clock signal is phase-lagging the Miller-encoded data signal and is at a constant value otherwise, and for producing a second synchronizing signal at a second output terminal, wherein said second synchronizing signal is a plurality of pulses when the clock signal is phase-leading the Miller-encoded data signal and is a constant value otherwise; integrator means responsive to said first and said second synchronizing signals for producing an integrated signal in response thereto; wherein said voltage-controlled oscillator means is responsive to said integrated signal for controlling the frequency and phase of said clock signal such that the clock signal and the Miller-encoded data signal are phase coherent.

Claim 3

The apparatus of claim 1 including means for providing a frequency reference signal that is supplied as an input to the processor means when the Miller-encoded data signal is not present.

Claim 4

Apparatus for producing a clock signal for use in decoding a Miller-encoded data signal, comprising: means for providing an output signal, wherein said output signal is in a first state, and goes to a second state for a predetermined duration at each transition of the Miller-encoded data signal; processor means for producing first and second control signals; integrator means responsive to said first and said second control signals for producing an integrated signal in response thereto; voltage-controlled oscillator means for controlling the phase and frequency of the clock signal in response to said integrated signal; wherein said processor means is responsive to said output and said clock signals; wherein said first control signal is set to remain in a first state when said output signal is in the first state, and wherein said first control signal goes to a second state when said output signal is in the second state while said clock signal undergoes a transition from a first to a second state; wherein said second control signal is set to remain in a first state when said clock signal is in the second state, and wherein said second control signal goes to a second state when said clock signal is in the first state while said output signal undergoes a transition from a second to a first state.

Claim 5

Apparatus for producing a clock signal for use in decoding a Miller-encoded data signal, comprising: means for providing an output signal, wherein said output signal is in a first state, and goes to a second state for a predetermined duration at each transition of the Miller-encoded data signal; processor means for producing first and second control signals; integrator means responsive to said first and said second control signals for producing an integrated signal in response thereto; voltage-controlled oscillator means for controlling the phase and frequency of the clock signal in response to said integrated signal; wherein said processor means is responsive to said output and said clock signals; wherein said first control signal is set to remain in a first state when said output signal is in the first state, and wherein said first control signal goes to a second state when said output signal is in the second state while said clock signal undergoes a transition from a first to a second state; wherein said second control signal is set to remain in a first state when said clock signal is in the second state, and wherein said second control signal goes to a second state when said clock signal is in the first state while said output signal undergoes a transition from a second to a first state.

Claim 6

Apparatus for producing a clock signal for decoding a Miller-encoded data signal, comprising: means for providing a first signal that undergoes a transition from a first to a second state at each transition of the Miller-encoded data signal; first flip-flop means including a set input terminal responsive to said first signal, wherein when said first signal goes to the first state, a first flip-flop signal is set to a first state; said first flip-flop means including a clock input terminal responsive to the clock signal; said first flip-flop means including a data input terminal responsive to said first signal, wherein said first flip-flop signal goes to the same state as said first signal at a prescribed point on the clock signal waveform; second flip-flop means including a set input terminal responsive to the clock signal, wherein a second flip-flop signal is set to a first state when the clock signal goes to the first state; said second flip-flop means responsive to said first signal at a clock input terminal thereof; said second flip-flop means including a data input terminal responsive to the clock signal, wherein said second flip-flop signal goes to the same state as the clock signal at a prescribed point on the waveform of said first signal; integrator means responsive to said first and second flip-flop signals for producing an integrated signal in response thereto; voltage-controlled oscillator means for controlling the phase and frequency of the clock signal in response to said integrated signal, wherein the clock signal is in phase with the Miller-encoded data signal.

Claim 7

Apparatus for producing a clock signal for decoding a Miller-encoded data signal, comprising: means for providing a first signal that undergoes a transition from a first to a second state at each transition of the Miller-encoded data signal; first flip-flop means including a set input terminal responsive to said first signal, wherein when said first signal goes to the first state, a first flip-flop signal is set to a first state; said first flip-flop means including a clock input terminal responsive to the clock signal; said first flip-flop means including a data input terminal responsive to said first signal, wherein said first flip-flop signal goes to the same state as said first signal at a prescribed point on the clock signal waveform; second flip-flop means including a set input terminal responsive to the clock signal, wherein a second flip-flop signal is set to a first state when the clock signal goes to the first state; said second flip-flop means responsive to said first signal at a clock input terminal thereof; said second flip-flop means including a data input terminal responsive to the clock signal, wherein said second flip-flop signal goes to the same state as the clock signal at a prescribed point on the waveform of said first signal; integrator means responsive to said first and second flip-flop signals for producing an integrated signal in response thereto; voltage-controlled oscillator means for controlling the phase and frequency of the clock signal in response to said integrated signal, wherein the clock signal is in phase with the Miller-encoded data signal.

Claim 8

The apparatus of claim 4 wherein the first flip-flop means includes a D flip-flop, and wherein the data input terminal includes a D input terminal.

Claim 9

The apparatus of claim 4 wherein the second flip-flop means includes a D flip-flop, and wherein the data input terminal includes a D input terminal.

Claim 10

Apparatus for decoding a data stream which has been encoded in the form of a Miller-encoded data signal, comprising: means for providing an output pulse of a predetermined duration at each transition of the Miller-encoded data signal; voltage-controlled oscillator means for producing a clock signal; processor means responsive to said clock signal and said output pulses for producing a first synchronizing signal at a first output terminal wherein said first synchronizing signal is a plurality of pulses when said clock signal is phase-lagging the Miller-encoded data signal and is at a constant value otherwise, and for producing a second synchronizing signal at a second output terminal, wherein said second synchronizing signal is a plurality of pulses when the clock signal is phase-leading the Miller-encoded data signal and is at a constant value otherwise; integrator means responsive to said first and said second synchronizing signals for producing an integrated signal in response thereto; wherein said voltage-controlled oscillator means is responsive to said integrated signal for controlling the frequency and phase of said clock signal such that said clock signal and the Miller-encoded data signal are phase coherent; decoder means responsive to said clock signal and the Miller-encoded data signal for recovering the data stream.

Claim 11

Apparatus for decoding a data stream which has been encoded in the form of a Miller-encoded data signal, comprising: means for providing an output pulse of a predetermined duration at each transition of the Miller-encoded data signal; voltage-controlled oscillator means for producing a clock signal; processor means responsive to said clock signal and said output pulses for producing a first synchronizing signal at a first output terminal wherein said first synchronizing signal is a plurality of pulses when said clock signal is phase-lagging the Miller-encoded data signal and is at a constant value otherwise, and for producing a second synchronizing signal at a second output terminal, wherein said second synchronizing signal is a plurality of pulses when the clock signal is phase-leading the Miller-encoded data signal and is at a constant value otherwise; integrator means responsive to said first and said second synchronizing signals for producing an integrated signal in response thereto; wherein said voltage-controlled oscillator means is responsive to said integrated signal for controlling the frequency and phase of said clock signal such that said clock signal and the Miller-encoded data signal are phase coherent; decoder means responsive to said clock signal and the Miller-encoded data signal for recovering the data stream.

Claim 12

Apparatus for demodulating a carrier signal modulated by a Miller-encoded data signal, and for decoding an information signal which has been encoded in the form of a Miller encoded data signal, said apparatus comprising: demodulator means responsive to said modulated carrier signal, said demodulator means for demodulating the modulated carrier signal to recover the Miller-encoded data signal; means for providing a frequency reference signal; detector means for detecting the presence of the modulated carrier signal; pulse-producing means selectably responsive to said frequency reference signal when the modulated carrier is not present, and selectably responsive to the Miller-encoded data signal when the modulated carrier signal is present, said pulse producing means for providing an output pulse of a predetermined duration when the signal input thereto undergoes a transition; voltage-controlled oscillator means for producing a clock signal; processor means responsive to said clock signal and said output pulses for producing a first plurality of pulses at a first output terminal when said clock signal is phase-lagging the Miller-encoded data signal, and for producing a second plurality of pulses at a second output terminal when said clock signal is phase-leading the Miller-encoded data signal; integrator means responsive to said first and said second plurality of pulses for producing an integrated signal in response thereto; wherein said voltage-controlled oscillator means is responsive to said integrated signal for controlling the frequency and phase of said clock signal such that said clock signal and the Miller-encoded data signal are phase coherent; decoder means responsive to said clock signal and the Miller-encoded data signal for recovering the information signal.

Claim 13

Apparatus for demodulating a carrier signal modulated by a Miller-encoded data signal, and for decoding an information signal which has been encoded in the form of a Miller encoded data signal, said apparatus comprising: demodulator means responsive to said modulated carrier signal, said demodulator means for demodulating the modulated carrier signal to recover the Miller-encoded data signal; means for providing a frequency reference signal; detector means for detecting the presence of the modulated carrier signal; pulse-producing means selectably responsive to said frequency reference signal when the modulated carrier is not present, and selectably responsive to the Miller-encoded data signal when the modulated carrier signal is present, said pulse producing means for providing an output pulse of a predetermined duration when the signal input thereto undergoes a transition; voltage-controlled oscillator means for producing a clock signal; processor means responsive to said clock signal and said output pulses for producing a first plurality of pulses at a first output terminal when said clock signal is phase-lagging the Miller-encoded data signal, and for producing a second plurality of pulses at a second output terminal when said clock signal is phase-leading the Miller-encoded data signal; integrator means responsive to said first and said second plurality of pulses for producing an integrated signal in response thereto; wherein said voltage-controlled oscillator means is responsive to said integrated signal for controlling the frequency and phase of said clock signal such that said clock signal and the Miller-encoded data signal are phase coherent; decoder means responsive to said clock signal and the Miller-encoded data signal for recovering the information signal.