Digital frame synchronizing circuit

Claim 1

In a digital information processing system in which digital information is formatted in a 3F delay modulation (Miller) code in which digital "1"s are represented as transitions at a particular location such as at the center of a bit cell and "0"s are represented as the absence of transitions at that location and by a transition at the start of a bit cell if the preceding bit was also a "0", such that allowable transitions occur at intervals corresponding to the durations of two bit cells, one and one-half bit cells and one bit cell respectively, thereby creating three respective frequencies f o , 11/2 f o and 2f o , and wherein a plurality of digital bits are serially combined to form a digital word and a plurality of words are serially combined to form a succession of frames making up a stream of digital bits, at least one word of each frame being dedicated to providing a frame sync code, a frame synchronizing circuit comprising means for generating a digital signal consisting of a sequence of digital bits 1-0-0-1 and for inhibiting a transition associated with the 0-0 transition in said 1-0-0-1 sequence, whereupon there is generated a digital signal block characterized by a pair of previously unallowed transitions occurring three bit cells apart, thus generating a fourth frequency, f 1 /2 which cannot naturally occur by any sequence of digital "1"s and "0"s, and means for inserting said digital block into the formatted digital data stream at a predetermined location to provide a frame sync signal which can be subsequently readily and simply detected and operated on by means responsive to said fourth frequency.