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US6562713B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method of protecting semiconductor areas while exposing a gate

Assignee: GlobalFoundries US Inc
•
Filing: 2002-02-19
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Granted: 2003-05-13
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Expires: 2022-02-19
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Abstract

Abstract Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed. Also disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.

Inventors

  • 👤 Michael P. Belyansky
  • 👤 Omer H. Dokumaci
  • 👤 Bruce B. Doris
  • 👤 Hussein I. Hanafi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:49
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/017; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0142; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 52 words
A method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising: depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed.
Claim 2
Independent Claim 52 words
A method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising: depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed.
Claim 3
Dependent Claim 38 words
The method of claim 1 wherein said deposition step further comprises: depositing said silicon compound to a thickness substantially the same height of said gate; and the removal of any excess said silicon compound from atop said gate.
Claim 4
Dependent Claim 35 words
The method of claim 2 wherein said removal step further comprises: depositing and patterning a resist layer to expose the top of said gate; etching away said excess silicon compound; and removing said resist layer.
Claim 5
Independent Claim 19 words
The method of step 1 wherein said depositing step is accomplished with a high density plasma chemical vapor deposition.
Claim 6
Independent Claim 19 words
The method of step 1 wherein said depositing step is accomplished with a high density plasma chemical vapor deposition.
Claim 7
Independent Claim 56 words
A method of processing short gates while protecting long gates on a semiconductor surface, the method comprising: depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates using a high density plasma chemical vapor deposition; and processing said semiconductor surface.
Claim 8
Independent Claim 56 words
A method of processing short gates while protecting long gates on a semiconductor surface, the method comprising: depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates using a high density plasma chemical vapor deposition; and processing said semiconductor surface.
Claim 9
Dependent Claim 13 words
The method of claim 5 , wherein said processing is a gate implant.
Claim 10
Independent Claim 62 words
A method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising: depositing a planarizing high density plasma layer of a silicon compound on a dielectric layer and abutting sidewalls of the gate using high density plasma chemical vapor deposition, wherein said plasma layer is substantially level with the top horizontal surface of the gate.
Claim 11
Independent Claim 62 words
A method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising: depositing a planarizing high density plasma layer of a silicon compound on a dielectric layer and abutting sidewalls of the gate using high density plasma chemical vapor deposition, wherein said plasma layer is substantially level with the top horizontal surface of the gate.
Claim 12
Dependent Claim 20 words
The method of claim 7 , wherein the silicon compound is from the group of silicon oxide and silicon nitride.
Claim 13
Dependent Claim 27 words
The method of claim 7 , wherein said deposition step further comprises: removing of any excess said silicon compound from the top horizontal surface of the gate.
Claim 14
Dependent Claim 36 words
The method of claim 9 , wherein said removal step further comprises; depositing and patterning a resist layer to expose the top of said gate; etching away said excess silicon compound; and removing said resist layer.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-05-12 2006-11-11 2007-05-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-05-12 2010-11-11 2011-05-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-05-12 2014-11-11 2015-05-13 $7700.00 Window Closed / Lapsed

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