Multiple finger polysilicon gate structure and method of making

Claim 2

A MOS transistor, comprising: a plurality of polysilicon gate regions; an interconnect comprising a first metal layer and a second metal layer, said first metal layer overlying and individually contacting each one of said plurality of polysilicon gate regions and said second metal layer overlying and contacting said first metal layer and forming a stack with said first metal layer to completely short together all of said plurality of polysilicon gate regions.

Claim 3

A MOS transistor according to claim 1, wherein said first metal comprises a refractory metal silicide or a doped polysilicon.

Claim 4

A MOS transistor according to claim 1, wherein said second metal comprises aluminum.

Claim 5

A MOS transistor according to claim 3, wherein said aluminum layer is between about 0.5 μm and 1 μm thick.

Claim 6

A MOS transistor according to claim 1, wherein said plurality of polysilicon gate regions has a plurality of fingers in a serpentine pattern and the fingers are separated by oxide-filled spaces.

Claim 7

A MOS transistor according to claim 5, wherein said fingers have a thickness k and said oxide-filled spaces have a width of ≦2 k and are formed from a conformal oxide layer having a thickness of k.

Claim 8

A MOS transistor fabricated according to a method comprising the steps of: a) defining a plurality of polysilicon gate regions; b) depositing a conformal oxide over each one of said plurality of polysilicon gate regions; c) anisotropically etching the conformal oxide with endpoint detection on each one of said plurality of polysilicon gate regions; d) forming a refractory metal silicide or doped polysilicon layer over and in individual contact with each one of said plurality of polysilicon gate regions; and e) depositing aluminum over and in contact with the refractory metal silicide or doped polysilicon layer to form a stack that completely shorts together all of said plurality of polysilicon gate regions.

Claim 9

A MOS transistor fabricated according to a method comprising the steps of: a) defining a plurality of polysilicon gate regions; b) depositing a conformal oxide over each one of said plurality of polysilicon gate regions; c) anisotropically etching the conformal oxide with endpoint detection on each one of said plurality of polysilicon gate regions; d) forming a refractory metal silicide or doped polysilicon layer over and in individual contact with each one of said plurality of polysilicon gate regions; and e) depositing aluminum over and in contact with the refractory metal silicide or doped polysilicon layer to form a stack that completely shorts together all of said plurality of polysilicon gate regions.

Claim 10

A MOS transistor fabricated according to a method comprising the steps of: a) forming a field oxide on a semiconductor wafer using a first mask to define a plurality of gate areas in an active device area on a substrate; b) patterning and etching a polysilicon layer through a second mask to form a plurality of polysilicon gate terminals of thickness k which together form a plurality of polysilicon fingers joined in a serpentine pattern and separated by spaces ≦2 k, wherein said second mask defines first, second, third and fourth regions, said first region defining where said fingers are formed from said polysilicon layer, said second region defining where said polysilicon is etched, but field oxide remains, said third region defining where said polysilicon is etched between said fingers to form said spaces, and said fourth region defining where said polysilicon is etched to open contact windows; c) stripping the photoresist remaining from step b); d) oxidizing the polysilicon to form oxide on said fingers; e) depositing a conformal oxide over said oxide on said fingers, in said spaces and in said fourth regions for contact windows; f) anisotropically etching said oxides formed in steps d) and e) with endpoint detection on said polysilicon; g) etching a metal layer of refractory metal silicide or doped polysilicon deposited on and in individual contact with said fingers and said oxide-filled spaces using a third mask so that the metal layer covers said active device area but does not cover said fourth regions; h) contact mask printing and etching said dielectric layer using a fourth mask to expose said metal layer and to open contacts; and i) etching an aluminum layer to form an interconnect with said metal layer using a fifth mask, said interconnect shorting together all of said plurality of polysilicon fingers at the same time.

Claim 11

A MOS transistor fabricated according to a method comprising the steps of: a) forming a field oxide on a semiconductor wafer using a first mask to define a plurality of gate areas in an active device area on a substrate; b) patterning and etching a polysilicon layer through a second mask to form a plurality of polysilicon gate terminals of thickness k which together form a plurality of polysilicon fingers joined in a serpentine pattern and separated by spaces ≦2 k, wherein said second mask defines first, second, third and fourth regions, said first region defining where said fingers are formed from said polysilicon layer, said second region defining where said polysilicon is etched, but field oxide remains, said third region defining where said polysilicon is etched between said fingers to form said spaces, and said fourth region defining where said polysilicon is etched to open contact windows; c) stripping the photoresist remaining from step b); d) oxidizing the polysilicon to form oxide on said fingers; e) depositing a conformal oxide over said oxide on said fingers, in said spaces and in said fourth regions for contact windows; f) anisotropically etching said oxides formed in steps d) and e) with endpoint detection on said polysilicon; g) etching a metal layer of refractory metal silicide or doped polysilicon deposited on and in individual contact with said fingers and said oxide-filled spaces using a third mask so that the metal layer covers said active device area but does not cover said fourth regions; h) contact mask printing and etching said dielectric layer using a fourth mask to expose said metal layer and to open contacts; and i) etching an aluminum layer to form an interconnect with said metal layer using a fifth mask, said interconnect shorting together all of said plurality of polysilicon fingers at the same time.