Method of fabricating wedge isolation transistors

Claim 1

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor structure having spaced, raised dielectric isolation regions defining an active region there between; selectively growing epitaxial silicon over said active region to form an SEG region; forming a dummy gate over said SEG region; selectively growing raised epitaxial silicon layers over said SEG region adjacent said dummy gate; removing said dummy gate to expose interior side walls of said raised epitaxial silicon layers; forming sidewall spacers on said exposed interior side walls of said raised epitaxial silicon layers; growing a gate oxide layer over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; depositing a polysilicon layer over the silicon semiconductor structure; planarizing said polysilicon layer to form a gate conductor over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; and removing said sidewall spacers.

Claim 2

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor structure having spaced, raised dielectric isolation regions defining an active region there between; selectively growing epitaxial silicon over said active region to form an SEG region; forming a dummy gate over said SEG region; selectively growing raised epitaxial silicon layers over said SEG region adjacent said dummy gate; removing said dummy gate to expose interior side walls of said raised epitaxial silicon layers; forming sidewall spacers on said exposed interior side walls of said raised epitaxial silicon layers; growing a gate oxide layer over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; depositing a polysilicon layer over the silicon semiconductor structure; planarizing said polysilicon layer to form a gate conductor over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; and removing said sidewall spacers.

Claim 11

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor structure having spaced, raised dielectric isolation regions defining an active region there between; selectively growing epitaxial silicon over said active region to form an SEG region; doping said SEG region to form a doped well; forming a dummy gate over said doped well; selectively growing raised epitaxial silicon layers over said doped well adjacent said dummy gate; doping said raised epitaxial silicon layers to form raised doped source/drain regions; removing said dummy gate to expose interior side walls of said raised doped source/drain regions; forming sidewall spacers on said exposed interior side walls of said raised doped source/ drain regions; growing a gate oxide layer over said doped well and between said sidewall spacers of said raised doped source/drain regions; depositing a polysilicon layer over the silicon semiconductor structure; planarizing said polysilicon layer to form a gate conductor over said doped well and between said sidewall spacers of said raised doped source/drain regions; removing said sidewall spacers; and forming source/drain extension implants in said doped well.

Claim 12

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor structure having spaced, raised dielectric isolation regions defining an active region there between; selectively growing epitaxial silicon over said active region to form an SEG region; doping said SEG region to form a doped well; forming a dummy gate over said doped well; selectively growing raised epitaxial silicon layers over said doped well adjacent said dummy gate; doping said raised epitaxial silicon layers to form raised doped source/drain regions; removing said dummy gate to expose interior side walls of said raised doped source/drain regions; forming sidewall spacers on said exposed interior side walls of said raised doped source/ drain regions; growing a gate oxide layer over said doped well and between said sidewall spacers of said raised doped source/drain regions; depositing a polysilicon layer over the silicon semiconductor structure; planarizing said polysilicon layer to form a gate conductor over said doped well and between said sidewall spacers of said raised doped source/drain regions; removing said sidewall spacers; and forming source/drain extension implants in said doped well.

Claim 19

A method of fabricating wedge isolation transistors, comprising the steps of: providing a silicon semiconductor structure having a first dielectric layer hereon; depositing and patterning a photoresist layer over said first dielectric layer; etching said first dielectric layer to form three raised isolation regions defining two active regions between adjacent said isolation regions raised; said isolation regions raised having sidewalls extending from uppermost silicon semiconductor structure at an angle from about 3 to 50°, removing said patterned photoresist layer; selectively growing epitaxial silicon over said active regions to form SEG regions; depositing and patterning a first photoresist N-type mask layer over one of said SEG regions defining a NMOS area under said first photoresist N-type mask layer and an exposed PMOS area not under said first photoresist N-type, mask layer; implanting N-type ions in said PMOS area SEG well region to form an N-type removing said first photoresist N-type mask layer; depositing and patterning a first photoresist P-type mask layer over said PMOS area; implanting P-type ions in said NMOS area SEG region to form an P-type well; removing said first photoresist P-type mask layer; forming dummy gates over said NMOS P-type well and PMOS N-type well; selectively growing epitaxial silicon over an unmasked NMOS P-type well and PMOS N-type well, to a height equal to the height of said isolation regions, to form raised NMOS source/drain regions over said NMOS P-type well and raised PMOS source/drain regions over said PMOS N-type well; depositing and patterning a second photoresist N-type mask layer over said PMOS area; implanting N-type ions in said raised NMOS source/drain regions; removing said second photoresist N-type mask layer; depositing and patterning a second photoresist P-type mask layer over said NMOS area; implanting P-type ions in said raised PMOS source/drain regions; removing said second photoresist P-type mask layer; removing said dummy gates from said NMOS P-type well and PMOS N-type well leaving a NMOS gate opening over said NMOS P-type well and a PMOS gate opening over said PMOS N-type well; selectively depositing dielectric spacer layers over said NMOS P-type well and said PMOS N-type well, filling said NMOS gate opening and said PMOS gate opening; etching said dielectric spacer layers to form NMOS and PMOS spacers adjacent said raised NMOS and raised PMOS source/drain regions; growing a gate oxide layer over NMOS P-type and PMOS N-type wells between said NMOS and PMOS spacers; depositing a polysilicon layer over the silicon semi conductor structure, filling NMOS gate opening and PMOS gate opening; planarizing said polysilicon layer level with the height of said raised NMOS and PMOS source/drain regions; removing said NMOS and PMOS spacers; implanting source/drain extensions within said NMOS P-type and PMOS N-type wells forming respective low doped and heavy doped regions; depositing and patterning a dielectric contact layer over said silicon semiconductor structure to form contact holes exposing said raised NMOS and PMOS source/drain regions; and depositing and planarizing metal in said contact holes to form metal contacts.

Claim 20

A method of fabricating wedge isolation transistors, comprising the steps of: providing a silicon semiconductor structure having a first dielectric layer hereon; depositing and patterning a photoresist layer over said first dielectric layer; etching said first dielectric layer to form three raised isolation regions defining two active regions between adjacent said isolation regions raised; said isolation regions raised having sidewalls extending from uppermost silicon semiconductor structure at an angle from about 3 to 50°, removing said patterned photoresist layer; selectively growing epitaxial silicon over said active regions to form SEG regions; depositing and patterning a first photoresist N-type mask layer over one of said SEG regions defining a NMOS area under said first photoresist N-type mask layer and an exposed PMOS area not under said first photoresist N-type, mask layer; implanting N-type ions in said PMOS area SEG well region to form an N-type removing said first photoresist N-type mask layer; depositing and patterning a first photoresist P-type mask layer over said PMOS area; implanting P-type ions in said NMOS area SEG region to form an P-type well; removing said first photoresist P-type mask layer; forming dummy gates over said NMOS P-type well and PMOS N-type well; selectively growing epitaxial silicon over an unmasked NMOS P-type well and PMOS N-type well, to a height equal to the height of said isolation regions, to form raised NMOS source/drain regions over said NMOS P-type well and raised PMOS source/drain regions over said PMOS N-type well; depositing and patterning a second photoresist N-type mask layer over said PMOS area; implanting N-type ions in said raised NMOS source/drain regions; removing said second photoresist N-type mask layer; depositing and patterning a second photoresist P-type mask layer over said NMOS area; implanting P-type ions in said raised PMOS source/drain regions; removing said second photoresist P-type mask layer; removing said dummy gates from said NMOS P-type well and PMOS N-type well leaving a NMOS gate opening over said NMOS P-type well and a PMOS gate opening over said PMOS N-type well; selectively depositing dielectric spacer layers over said NMOS P-type well and said PMOS N-type well, filling said NMOS gate opening and said PMOS gate opening; etching said dielectric spacer layers to form NMOS and PMOS spacers adjacent said raised NMOS and raised PMOS source/drain regions; growing a gate oxide layer over NMOS P-type and PMOS N-type wells between said NMOS and PMOS spacers; depositing a polysilicon layer over the silicon semi conductor structure, filling NMOS gate opening and PMOS gate opening; planarizing said polysilicon layer level with the height of said raised NMOS and PMOS source/drain regions; removing said NMOS and PMOS spacers; implanting source/drain extensions within said NMOS P-type and PMOS N-type wells forming respective low doped and heavy doped regions; depositing and patterning a dielectric contact layer over said silicon semiconductor structure to form contact holes exposing said raised NMOS and PMOS source/drain regions; and depositing and planarizing metal in said contact holes to form metal contacts.

Claim 22

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between; selectively growing epitaxial silicon over said active region to form an SEG region; forming a dummy gate over said SEG region; selectively growing raised epitaxial silicon layers over said SEG region adjacent said dummy gate; removing said dummy gate to expose interior side walls of said raised epitaxial silicon layers; forming sidewall spacers on said exposed interior side walls of said raised epitaxial silicon layers; growing a gate oxide layer over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; depositing a polysilicon layer over the silicon semiconductor structure; planarizing said polysilicon layer to form a gate conductor over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; and removing said sidewall spacers; whereby the transistor is fabricated without the use of a high density plasma process or a chemical-mechanical polishing process.

Claim 23

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between; selectively growing epitaxial silicon over said active region to form an SEG region; forming a dummy gate over said SEG region; selectively growing raised epitaxial silicon layers over said SEG region adjacent said dummy gate; removing said dummy gate to expose interior side walls of said raised epitaxial silicon layers; forming sidewall spacers on said exposed interior side walls of said raised epitaxial silicon layers; growing a gate oxide layer over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; depositing a polysilicon layer over the silicon semiconductor structure; planarizing said polysilicon layer to form a gate conductor over said SEG region and between said sidewall spacers of said raised epitaxial silicon layers; and removing said sidewall spacers; whereby the transistor is fabricated without the use of a high density plasma process or a chemical-mechanical polishing process.