US6553452B2 — Synchronous memory device having a temperature re…

Claim 1

Independent Claim 58 words

A synchronous dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises: input receiver circuitry to sample an externally provided value that is representative of a range of temperatures; and a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.

Claim 2

Dependent Claim 58 words

A synchronous dynamic random access memory device having an array of dynamic memory cells, wherein the memory device comprises: input receiver circuitry to sample an externally provided value that is representative of a range of temperatures; and a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.

Claim 3

Dependent Claim 38 words

The memory device of claim 1 , further including a register to store data transfer rate information, wherein an internal circuit is adjusted based on the data transfer rate information and the value stored in the programmable register.

Claim 4

Dependent Claim 33 words

The memory device of claim 2 , further including a clock synchronization circuit to receive an external clock signal and synchronize outputting of data from the memory device with the external clock signal.

Claim 5

Dependent Claim 26 words

The memory device of claim 3 , wherein the clock synchronization circuit includes one of a delay locked loop circuit and a phase locked loop circuit.

Claim 6

Dependent Claim 76 words

The memory device of claim 3 , wherein the clock synchronization circuit includes: a phase detector to generate information representative of a difference in phase between the external clock signal and an internal clock signal; and a delay circuit to generate the internal clock signal, wherein an amount of delay of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal.

Claim 7

Dependent Claim 36 words

The memory device of claim 3 , wherein the programmable register is coupled to the clock synchronization circuit, and wherein the clock synchronization circuit is adjusted in accordance with the value stored within the programmable register.

Claim 8

Dependent Claim 35 words

The memory device of claim 3 , wherein the clock synchronization circuit includes a mixer circuit to vary a phase of an internal clock signal in response to the value stored in the programmable register.

Claim 9

Dependent Claim 25 words

The memory device of claim 1 , further including decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

Claim 10

Dependent Claim 57 words

The memory device of claim 1 , further including a register to store information indicative of a length of an external signal line coupled to the memory device, wherein the memory device tunes an internal circuit based on the value stored within the programmable register and the information indicative of the length of the external signal line.

Claim 11

Dependent Claim 38 words

The memory device of claim 1 , further including a register to store supply voltage information, wherein the memory device tunes an internal circuit based on the supply voltage information and the value stored within the programmable register.

Claim 12

Independent Claim 61 words

A method of controlling a synchronous dynamic random access memory device by a memory controller, wherein the method comprises: in the memory controller, generating information indicative of a temperature range; and providing the information indicative of the temperature range to the memory device, wherein the memory device receives the information and stores the information in a register on the memory device.

Claim 13

Independent Claim 61 words

A method of controlling a synchronous dynamic random access memory device by a memory controller, wherein the method comprises: in the memory controller, generating information indicative of a temperature range; and providing the information indicative of the temperature range to the memory device, wherein the memory device receives the information and stores the information in a register on the memory device.

Claim 14

Dependent Claim 26 words

The method of claim 11 , wherein the information indicative of the temperature range is provided to the memory device during initialization of the memory device.

Claim 15

Dependent Claim 41 words

The method of claim 11 , further including providing information indicative of a data transfer rate to the memory device, wherein the memory device times internal circuitry based on the temperature information and the information indicative of the data transfer rate.

Claim 16

Dependent Claim 78 words

The method of claim 11 , wherein the memory controller is coupled to the memory device via an external signal line, the method further including: in the controller device, detecting the length of the external signal line; and providing a value representative of the length of the external signal line to the memory device, wherein the memory device tunes internal circuitry based on the temperature information and the value representative of the length of the external signal line.

Claim 17

Dependent Claim 39 words

The method of claim 11 , further including: detecting supply voltage information; and providing the supply voltage information to the memory device, wherein the memory device tunes internal circuitry based on the temperature information and the supply voltage information.

Claim 18

Independent Claim 44 words

A method of operation in a memory device that includes a plurality of memory cells, the method comprising: receiving, from a controller, a value which is representative of a range of temperatures; and storing the value in a programmable register on the memory device.

Claim 19

Independent Claim 44 words

A method of operation in a memory device that includes a plurality of memory cells, the method comprising: receiving, from a controller, a value which is representative of a range of temperatures; and storing the value in a programmable register on the memory device.

Claim 20

Dependent Claim 19 words

The method of claim 16 , wherein the value is issued to the memory device during an initialization period.

Claim 21

Dependent Claim 24 words

The method of claim 16 , further including tuning an internal circuit based on the value that is representative of a range of temperatures.

Claim 22

Dependent Claim 31 words

The method of claim 16 , further including: decoding the value to generate an internal control signal; and adjusting an internal clock synchronization circuit in response to the internal control signal.

Claim 23

Dependent Claim 23 words

The method of claim 19 , wherein adjusting the internal clock synchronization circuit includes adjusting a phase mixer in accordance with the value.

Claim 24

Dependent Claim 38 words

The method of claim 19 , wherein the clock synchronization circuit is a delay lock loop circuit, wherein the delay lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal.

Claim 25

Independent Claim 37 words

The method of 19 , wherein the clock synchronization circuit is a phase lock loop circuit, wherein the phase lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal.

Claim 26

Independent Claim 37 words

The method of 19 , wherein the clock synchronization circuit is a phase lock loop circuit, wherein the phase lock loop circuit generates an internal clock signal having a predetermined timing relationship with an external clock signal.

Claim 27

Dependent Claim 45 words

The method of claim 16 , further including: receiving a value that is representative of one of a plurality of data transfer rates; and tuning an internal circuit based on the value that is representative of the one of the plurality of data transfer rates.

Claim 28

Dependent Claim 35 words

The method of claim 16 , further including adjusting a locking frequency range of an internal clack synchronization circuit, wherein the locking frequency range is adjusted based on the value stored in the programmable register.

Claim 29

Dependent Claim 37 words

The method of claim 16 , further including generating an internal clock signal having a predetermined phase relationship with an external clock signal, wherein the internal clock signal synchronizes the outputting of data from the memory device.

Claim 30

Dependent Claim 48 words

The method of claim 25 , further including: detecting a phase differential between the external clock signal and the internal clock signal; generating the internal clock signal using a plurality of delay elements; and varying the amount of delay in each delay element based on the phase differential.

Claim 31

Dependent Claim 25 words

The method of claim 16 , further including: receiving supply voltage information from the controller; and storing the supply voltage information within the memory device.

Claim 32

Dependent Claim 41 words

The method of claim 16 , further including: receiving information which is representative of a data transfer rate from the controller; and storing the information which is representative of a data transfer rate in a register disposed within the memory device.

Claim 33

Dependent Claim 148 words

An integrated circuit device having an array of memory cells, wherein the integrated circuit device comprises: a programmable register to store a value that is representative of a range of temperatures; and a clock synchronization circuit to receive an external clock signal and generate an internal clock signal, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register, wherein the clock synchronization circuit includes: a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and a delay element to generate the internal clock signal, wherein an amount of delay of the delay element is varied based on the information representative of the difference in phase between the external clock signal and the internal clock signal; and output driver circuitry to output data in response to the internal clock signal.

Claim 34

Dependent Claim 148 words

An integrated circuit device having an array of memory cells, wherein the integrated circuit device comprises: a programmable register to store a value that is representative of a range of temperatures; and a clock synchronization circuit to receive an external clock signal and generate an internal clock signal, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register, wherein the clock synchronization circuit includes: a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and a delay element to generate the internal clock signal, wherein an amount of delay of the delay element is varied based on the information representative of the difference in phase between the external clock signal and the internal clock signal; and output driver circuitry to output data in response to the internal clock signal.

Claim 35

Dependent Claim 38 words

The integrated circuit device of claim 29 , wherein the clock synchronization circuit further includes a mixer circuit to vary a phase range of the internal clock signal in response to the value stored in the programmable register.

Claim 36

Dependent Claim 25 words

The integrated circuit device of claim 29 further including decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

Claim 37

Dependent Claim 63 words

The integrated circuit device of claim 29 , further including a register to store information that is representative of a length of an external signal line coupled to the integrated circuit device, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register and the information that is representative of the length of the external signal line.

Claim 38

Dependent Claim 39 words

The integrated circuit device of claim 29 , further including a register to store supply voltage information, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register and the supply voltage information.

Claim 39

Dependent Claim 41 words

The integrated circuit device of claim 29 , further including a register to store data transfer rate information, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register and the data transfer rate information.

Claim 40

Dependent Claim 151 words

An integrated circuit device having an array of memory cells, wherein the integrated circuit device comprises: a programmable register to store a value that is representative of the range of temperatures; and a clock synchronization circuit to receive an external clock signal and generate an internal clock signal, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register, wherein the clock synchronization circuit includes: a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and an oscillator circuit, coupled to the phase detector, to generate the internal clock signal, wherein a phase of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal; and output driver circuitry to output data in response to the internal clock signal.

Claim 41

Dependent Claim 151 words

An integrated circuit device having an array of memory cells, wherein the integrated circuit device comprises: a programmable register to store a value that is representative of the range of temperatures; and a clock synchronization circuit to receive an external clock signal and generate an internal clock signal, wherein the clock synchronization circuit is adjusted in accordance with the value stored in the programmable register, wherein the clock synchronization circuit includes: a phase detector to generate information representative of a difference in phase between the external clock signal and the internal clock signal; and an oscillator circuit, coupled to the phase detector, to generate the internal clock signal, wherein a phase of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal; and output driver circuitry to output data in response to the internal clock signal.

Claim 42

Dependent Claim 18 words

The integrated circuit device of claim 35 , wherein the clock synchronization circuit further includes a mixer circuit.

Claim 43

Dependent Claim 26 words

The integrated circuit device of claim 35 , further including decoder circuitry coupled to the programmable register to decode the value stored within the programmable register.

Claim 44

Dependent Claim 30 words

The integrated circuit device of claim 35 , further including a circuit to store information indicative of a length of an external signal line coupled to the integrated circuit device.

Claim 45

Dependent Claim 17 words

The integrated circuit device of claim 35 , further including a circuit to store supply voltage information.

Claim 46

Dependent Claim 18 words

The integrated circuit device of claim 35 , further including a circuit to store data transfer rate information.

Claim 47

Dependent Claim 97 words

A synchronous integrated circuit memory device having an array of dynamic memory cells, wherein the memory device comprises: transceiver circuitry including: a plurality of input receivers to receive an externally provided value that is representative of a range of temperatures; and a plurality of output drivers to transmit data; a locked loop circuit, coupled to the plurality of output drivers, to synchronize transmission of data from the memory device with an external clock signal; and a programmable register, coupled to the plurality of input receivers, to store the value that is representative of a range of temperatures.

Claim 48

Dependent Claim 97 words

A synchronous integrated circuit memory device having an array of dynamic memory cells, wherein the memory device comprises: transceiver circuitry including: a plurality of input receivers to receive an externally provided value that is representative of a range of temperatures; and a plurality of output drivers to transmit data; a locked loop circuit, coupled to the plurality of output drivers, to synchronize transmission of data from the memory device with an external clock signal; and a programmable register, coupled to the plurality of input receivers, to store the value that is representative of a range of temperatures.

Claim 49

Dependent Claim 92 words

The memory device of claim 41 , wherein the transmission of data is synchronized to the external clock signal using an internal clock signal, wherein the locked loop circuit further includes: a phase detector to generate information representative of a phase difference between the external clock signal and the internal clock signal; and a delay element to generate the internal clock signal, wherein an amount of delay of the delay element is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal.

Claim 50

Dependent Claim 36 words

The memory device of claim 42 , wherein the clock synchronization circuit further includes a mixer circuit to vary a phase of the internal clock signal in response to the value stored in the programmable register.

Claim 51

Dependent Claim 96 words

The memory device of claim 41 , wherein the transmission of data is synchronized to the external clock signal using an internal clock signal, wherein the locked loop circuit further includes: a phase detector to generate information representative of a phase difference between the external clock signal and the internal clock signal; and an oscillator circuit, coupled to the phase detector, to generate the internal clock signal, wherein a phase of the internal clock signal is varied based on the information representative of the phase difference between the external clock signal and the internal clock signal.

Claim 52

Dependent Claim 37 words

The memory device of claim 44 , wherein the locked loop circuit further includes a mixer circuit to vary a phase range of the internal clock signal in response to the value stored in the programmable register.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-04-21	2006-10-21	2007-04-22	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-04-21	2010-10-21	2011-04-22	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-04-21	2014-10-21	2015-04-22	$7700.00	Window Closed / Lapsed

Synchronous memory device having a temperature register

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