Method and apparatus for generating and synchronizing a plurality of digital signals

Claim 1

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising: a. a clock generating circuit comprising: (1) an input for receiving a master clock signal having a predetermined range of frequencies; (2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals; and (3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; and b. a timing multiplexer, coupled to receive the internal clock signals from the clock generating circuit, the timing multiplexer comprising: (1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising: (a) a data channel input for receiving a predetermined one of the data bits; (b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information; and (c) an output port for coupling an output signal representative of the predetermined one of the data bit to the HME at the predetermined time; and (2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal.

Claim 2

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising: a. a clock generating circuit comprising: (1) an input for receiving a master clock signal having a predetermined range of frequencies; (2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals; and (3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; and b. a timing multiplexer, coupled to receive the internal clock signals from the clock generating circuit, the timing multiplexer comprising: (1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising: (a) a data channel input for receiving a predetermined one of the data bits; (b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information; and (c) an output port for coupling an output signal representative of the predetermined one of the data bit to the HME at the predetermined time; and (2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal.

Claim 3

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising: a. at least two clock generating circuits, each clock generating circuit comprising: (1) an input for receiving a master clock signal having a predetermined first period; (2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals; and (3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; and b. at least two timing multiplexers, coupled to receive the internal clock signals from one of the clock generating circuits, each timing multiplexer comprising: (1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising: (a) a data channel input for receiving a predetermined one of the data bits; (b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information; and (c) an output port for coupling an output signal representative of the data bit to the HME at the predetermined time; and (2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal, wherein the throughput delays for each of the timing multiplexers need not be identical.

Claim 4

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising: a. at least two clock generating circuits, each clock generating circuit comprising: (1) an input for receiving a master clock signal having a predetermined first period; (2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals; and (3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; and b. at least two timing multiplexers, coupled to receive the internal clock signals from one of the clock generating circuits, each timing multiplexer comprising: (1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising: (a) a data channel input for receiving a predetermined one of the data bits; (b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information; and (c) an output port for coupling an output signal representative of the data bit to the HME at the predetermined time; and (2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal, wherein the throughput delays for each of the timing multiplexers need not be identical.

Claim 5

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising: a. at least two clock generating circuits, each clock generating circuit comprising: (1) an input for receiving a master clock signal having a predetermined first period; (2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals; and (3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; b. at least two timing multiplexers, each coupled to receive the internal clock signals from a respective one of the clock generating circuits, each timing multiplexer comprising: (1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising: (a) a data channel input for receiving a predetermined one of the data bits; (b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information; and (c) an output port for coupling an output signal representative of the data bit to the HME at the predetermined time; (2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal, wherein the throughput delays for each of the timing multiplexers need not be identical; and c. a timing adjustment control circuit coupled to each of the timing multiplexers for selectively delaying the data bits as input signals in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.

Claim 6

An apparatus for generating and synchronizing a plurality of precisely timed digital signals, the apparatus coupled to receive a plurality of data bits and timing information for each of the data bits, the apparatus for providing each one of the data bits to a Hardware Modeling Element (HME) at a predetermined time specified by the timing information, the apparatus comprising: a. at least two clock generating circuits, each clock generating circuit comprising: (1) an input for receiving a master clock signal having a predetermined first period; (2) a divider circuit coupled to the input for receiving the master clock signal and for generating therefrom a plurality of evenly timed internal clock signals; and (3) a phase adjusting circuit for receiving a feedback control signal and for adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; b. at least two timing multiplexers, each coupled to receive the internal clock signals from a respective one of the clock generating circuits, each timing multiplexer comprising: (1) a plurality of data channels, each having an approximately same throughput delay within each data channel, each data channel comprising: (a) a data channel input for receiving a predetermined one of the data bits; (b) a controller for receiving the timing information for the predetermined one of the data bits and for selecting one of the internal clock signals which most closely matches the timing information; and (c) an output port for coupling an output signal representative of the data bit to the HME at the predetermined time; (2) a dummy channel having the sensed throughput delay which approximates the approximately same throughput delay, the dummy channel having a dummy input coupled to receive a first one of the internal clock signals and a dummy output coupled to provide the feedback control signal, wherein the throughput delays for each of the timing multiplexers need not be identical; and c. a timing adjustment control circuit coupled to each of the timing multiplexers for selectively delaying the data bits as input signals in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.

Claim 7

A method of generating and synchronizing a plurality of precisely timed digital signals, and providing the digital signals to a Hardware Modeling Element (HME) at a predetermined time, the method comprising: a. receiving a plurality of data bits and timing information for each of the data bits; b. receiving a master clock signal having a predetermined range of frequencies; c. generating a plurality of evenly timed internal clock signals from the master clock signal; d. receiving a feedback control signal and adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; e. coupling the internal clock signals to a plurality of data channels, each having an approximately same throughput delay within each data channel; f. receiving a predetermined one of the data bits; g. selecting one of the internal clock signals which most closely matches the timing information for the predetermined one of the data bits; h. coupling a first one of the internal clock signals to a dummy channel having the sensed delay which approximates the approximately same throughput delay; and i. providing an output of the dummy channel as the feedback control signal.

Claim 8

A method of generating and synchronizing a plurality of precisely timed digital signals, and providing the digital signals to a Hardware Modeling Element (HME) at a predetermined time, the method comprising: a. receiving a plurality of data bits and timing information for each of the data bits; b. receiving a master clock signal having a predetermined range of frequencies; c. generating a plurality of evenly timed internal clock signals from the master clock signal; d. receiving a feedback control signal and adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; e. coupling the internal clock signals to a plurality of data channels, each having an approximately same throughput delay within each data channel; f. receiving a predetermined one of the data bits; g. selecting one of the internal clock signals which most closely matches the timing information for the predetermined one of the data bits; h. coupling a first one of the internal clock signals to a dummy channel having the sensed delay which approximates the approximately same throughput delay; and i. providing an output of the dummy channel as the feedback control signal.

Claim 9

A method of generating and synchronizing a plurality of precisely timed digital signals, and providing the digital signals to a Hardware Modeling Element (HME) at a predetermined time, the method comprising: a. receiving a plurality of data bits and timing information for each of the data bits; b. receiving a master clock signal having a predetermined first period; c. generating a plurality of evenly timed internal clock signals from the master clock signal; d. receiving a feedback control signal and adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; e. coupling the internal clock signals to one group of a plurality of data channels, each of the data channels in each group having an approximately same throughput delay within each data channel; f. receiving a predetermined one of the data bits; g. selecting one of the internal clock signals which most closely matches the timing information for the predetermined one of the data bits; h. coupling a first one of the internal clock signals to a dummy channel having the sensed delay which approximates the approximately same throughput delay; and i. providing an output of the dummy channel as the feedback control signal.

Claim 10

A method of generating and synchronizing a plurality of precisely timed digital signals, and providing the digital signals to a Hardware Modeling Element (HME) at a predetermined time, the method comprising: a. receiving a plurality of data bits and timing information for each of the data bits; b. receiving a master clock signal having a predetermined first period; c. generating a plurality of evenly timed internal clock signals from the master clock signal; d. receiving a feedback control signal and adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; e. coupling the internal clock signals to one group of a plurality of data channels, each of the data channels in each group having an approximately same throughput delay within each data channel; f. receiving a predetermined one of the data bits; g. selecting one of the internal clock signals which most closely matches the timing information for the predetermined one of the data bits; h. coupling a first one of the internal clock signals to a dummy channel having the sensed delay which approximates the approximately same throughput delay; and i. providing an output of the dummy channel as the feedback control signal.

Claim 11

A method of generating and synchronizing a plurality of precisely timed digital signals, and providing the digital signals to a Hardware Modeling Element (HME) at a predetermined time, the method comprising: a. receiving a plurality of data bits and timing information for each of the data bits; b. receiving a master clock signal having a predetermined first period; c. generating a plurality of evenly timed internal clock signals from the master clock signal; d. receiving a feedback control signal and adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; e. coupling the internal clock signals to one group of a plurality of data channels, each of the data channels in the group having an approximately same throughput delay within each data channel; f. receiving a predetermined one of the data bits; g. selecting one of the internal clock signals which most closely matches the timing information for the predetermined one of the data bits; h. coupling a first one of the internal clock signals to a dummy channel having the sensed delay which approximates the approximately same throughput delay; i. providing an output of the dummy channel as the feedback control signal; and j. adjusting the step of selecting to compensate for different throughput delays in different groups.

Claim 12

A method of generating and synchronizing a plurality of precisely timed digital signals, and providing the digital signals to a Hardware Modeling Element (HME) at a predetermined time, the method comprising: a. receiving a plurality of data bits and timing information for each of the data bits; b. receiving a master clock signal having a predetermined first period; c. generating a plurality of evenly timed internal clock signals from the master clock signal; d. receiving a feedback control signal and adjusting a phase delay within the plurality of internal clock signals in accordance with a sensed throughput delay; e. coupling the internal clock signals to one group of a plurality of data channels, each of the data channels in the group having an approximately same throughput delay within each data channel; f. receiving a predetermined one of the data bits; g. selecting one of the internal clock signals which most closely matches the timing information for the predetermined one of the data bits; h. coupling a first one of the internal clock signals to a dummy channel having the sensed delay which approximates the approximately same throughput delay; i. providing an output of the dummy channel as the feedback control signal; and j. adjusting the step of selecting to compensate for different throughput delays in different groups.