Simple digital method for controlling digital signals to achieve synchronization

Claim 1

A digital method for controlling digital signals so as to achieve synchronization comprising the steps of: obtaining a gate array logic circuit for controlling a plurality of identical signal generators connected to said gate array logic circuit, said gate array containing a plurality of comparison means, each containing a comparison terminal and a reference terminal so as to cause a plurality of synchronous signals sent out from said signal generators, respectively, to be compared with each other during each clock cycle, each of said comparison terminals being connected to a signal generator whose signal is to be synchronized, and said reference terminals being respectively connected to at least two of said signal generators; sending a clock signal which is used as an input to each respective pair of said comparison terminal and said reference terminal; wherein said gate array logic circuit further comprising an output gate, which is provided to generate a plurality of gate outputs based on a operation of said gate array logic circuit, each of said gate outputs being arranged to pass through an OR-gate so as to disable said input clock signal from one of said signal generators connected to a specific comparison terminal so as to achieve synchronization; said operation of said gate array logic circuit comprising the following sub-steps: (a) performing a waiting procedure for each comparison means until it is received that said comparison terminal is "1" and said reference terminal is "0", then move to a gate procedure; otherwise, continuing said waiting procedure; (b) performing a gate procedure by continuously sending out a "1" gate signal from said comparison means, i.e., said gate being set at "1" state, until a "1" signal is received at said reference terminal is "1", then moving to a reset procedure; (c) performing a reset procedure by sending out a "0" gate output, so as to set said gate being set at "0" state, said reset procedures continues until said reference terminal is "0", then going back to said waiting procedure; (d) wherein a "0" gate signal indicating that system synchronization is normal, thus no disable action is taken, and a "1" gate signal indicating that one of said signal generators connected to a specific comparison reference is too fast and a disable action is taken.