Patent US6512395B1 successfully refreshed from Google Patents.
US6512395B1
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Configurable memory for programmable logic circuits
Assignee: Monterey Research LLC
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Filing: 2001-12-18
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Granted: 2003-01-28
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Expires: 2021-12-18
Abstract
Abstract An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
Inventors
- 👤 Timothy M. Lacey
- 👤 David L. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
51 words
An apparatus comprising: a memory device configured to: receive one or more inputs from a first bus and a second bus; present one or more outputs to said first bus and said second bus; and operate in one or more modes in response to information stored in a programmable logic circuit.
Claim 2
Independent Claim
51 words
An apparatus comprising: a memory device configured to: receive one or more inputs from a first bus and a second bus; present one or more outputs to said first bus and said second bus; and operate in one or more modes in response to information stored in a programmable logic circuit.
Claim 3
Dependent Claim
19 words
The apparatus according to claim 1 , wherein said apparatus comprises a configurable memory in a programmable logic device.
Claim 4
Dependent Claim
18 words
The apparatus according to claim 1 , wherein said memory device further comprises an asynchronous dual port RAM.
Claim 5
Dependent Claim
33 words
The apparatus according to claim 3 , wherein said memory device further comprises an input multiplexer configured to select input signals to said asynchronous dual port RAM in response to said control signals.
Claim 6
Dependent Claim
27 words
The apparatus according to claim 3 , wherein said memory device further comprises an output multiplexer configured to select output signals in response to said control signals.
Claim 7
Dependent Claim
21 words
The apparatus according to claim 2 , wherein said first bus comprises a first routing channel of said programmable logic device.
Claim 8
Dependent Claim
21 words
The apparatus according to claim 2 , wherein said second bus comprises a second routing channel of said programmable logic device.
Claim 9
Dependent Claim
22 words
The apparatus according to claim 1 , wherein a plurality of said memory devices are cascaded to form a larger memory block.
Claim 10
Dependent Claim
18 words
The apparatus according to claim 1 , wherein said memory device is configurable as a synchronous FIFO memory.
Claim 11
Dependent Claim
19 words
The apparatus according to claim 1 , wherein said memory device is configurable as a synchronous dual port memory.
Claim 12
Dependent Claim
19 words
The apparatus according to claim 1 , wherein said memory device is configurable as an asynchronous dual port memory.
Claim 13
Dependent Claim
19 words
The apparatus according to claim 1 , wherein said memory device is configured using a JTAG programming standard STAPL.
Claim 14
Dependent Claim
15 words
The apparatus according to claim 1 , wherein said memory device comprises dedicated FIFO logic.
Claim 15
Dependent Claim
16 words
The apparatus according to claim 1 , wherein said memory device comprises dedicated dual port logic.
Claim 16
Dependent Claim
30 words
The apparatus according to claim 1 , wherein said memory device is configurable to connect directly to one or more inputs or outputs through said first and/or said second busses.
Claim 17
Dependent Claim
51 words
The apparatus according to claim 2 , wherein: said programmable logic device comprises a first routing channel run parallel to a first axis and a second routing channel run parallel to a second axis; and said memory device is connected to said first routing channel and to said second routing channel.
Claim 18
Dependent Claim
58 words
A memory device comprising: means for receiving one or more inputs from a first bus and a second bus; means for presenting one or more outputs to said first bus and said second bus; means for operating in one or more modes in response to one or more control signals; and means for programmably generating said control signals.
Claim 19
Dependent Claim
58 words
A memory device comprising: means for receiving one or more inputs from a first bus and a second bus; means for presenting one or more outputs to said first bus and said second bus; means for operating in one or more modes in response to one or more control signals; and means for programmably generating said control signals.
Claim 20
Independent Claim
70 words
A method for providing a memory in a programmable logic device comprising the steps of: receiving one or more inputs to said memory from a first bus and a second bus; presenting one or more outputs from said memory to said first bus and said second bus; and operating said memory in one or more modes in response to one or more control signals generated by said programmable logic device.
Claim 21
Independent Claim
70 words
A method for providing a memory in a programmable logic device comprising the steps of: receiving one or more inputs to said memory from a first bus and a second bus; presenting one or more outputs from said memory to said first bus and said second bus; and operating said memory in one or more modes in response to one or more control signals generated by said programmable logic device.
References Cited (Backward Citations)
US5451887A
Cited
US4878200A
Cited
US5422823A
Cited
US5144582A
Cited
US5136188A
Cited
US5280202A
Cited
US5384745A
Cited
US5455525A
Cited
US5631577A
Cited
US5537057A
Cited
US6049223A
Cited
US5689195A
Cited
US5811987A
Cited
US5521529A
Cited
US5781030A
Cited
US5818254A
Cited
US6049225A
Cited
US6130552A
Cited
US5587945A
Cited
US5848285A
Cited
US5799176A
Cited
US5646901A
Cited
US5977791A
Cited
US6097211A
Cited
US5933023A
Cited
US6058452A
Cited
US5966027A
Cited
US6201407B1
Cited
US6191998B1
Cited
US6137308A
Cited
US6181163B1
Cited
US6134181A
Cited
US6271679B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-01-27 | 2006-07-29 | 2007-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-27 | 2010-07-29 | 2011-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-27 | 2014-07-29 | 2015-01-28 | $7700.00 | Window Closed / Lapsed |