Configuration memory integrated circuit

Claim 2

An integrated circuit memory comprising: a memory array; an address counter coupled to the memory array; a first output terminal that outputs a logic state depending on the value of the address counter; a data out port coupled to said memory array; and JTAG circuitry for receiving a JTAG instruction and controlling operation of said integrated circuit memory according to said JTAG instruction.

Claim 3

The integrated circuit memory of claim 1 wherein said memory array is programmable via said JTAG circuitry.

Claim 4

The integrated circuit memory of claim 1 wherein said memory array is in-system programmable using said JTAG circuitry.

Claim 5

The integrated circuit memory of claim 1 wherein said memory array stores configuration data for configuring a programmable logic device.

Claim 6

The integrated circuit memory of claim 4 wherein said configuration data is transferable responsive to receipt of said JTAG instruction.

Claim 7

The integrated circuit memory of claim 1 wherein said memory array further comprises a second output terminal being changed from a first logic state to a second logic state responsive to receipt of said JTAG instruction.

Claim 8

A configuration memory for use in storing information comprising: a clock signal providing a clocking event; a memory array for storing said information; first and second input control lines; an address counter, said address counter providing an address to said memory array, said address counter being enabled responsive to said first and second input control lines, said address counter being reset responsive to said second input control line, whereby when said address counter is enabled, said address counter is advanced to the next address in said memory array with each clocking event; a first output terminal; decode logic, said decode logic causing said first output terminal to change from a first logic state to a second logic state when said address counter has a value corresponding to an address of a last item of information in said memory array; a data out port through which said information is transferable out of said configuration memory; and JTAG circuitry, said JTAG circuitry being capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction.

Claim 9

A configuration memory for use in storing information comprising: a clock signal providing a clocking event; a memory array for storing said information; first and second input control lines; an address counter, said address counter providing an address to said memory array, said address counter being enabled responsive to said first and second input control lines, said address counter being reset responsive to said second input control line, whereby when said address counter is enabled, said address counter is advanced to the next address in said memory array with each clocking event; a first output terminal; decode logic, said decode logic causing said first output terminal to change from a first logic state to a second logic state when said address counter has a value corresponding to an address of a last item of information in said memory array; a data out port through which said information is transferable out of said configuration memory; and JTAG circuitry, said JTAG circuitry being capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction.

Claim 10

The configuration memory of claim 7 wherein said memory array is programmable via said JTAG port.

Claim 11

The configuration memory of claim 7 wherein said memory array is in-system programmable.

Claim 12

The configuration memory of claim 7 wherein said information is configuration data for configuring programmable logic devices.

Claim 13

The configuration memory of claim 9 further comprising: a first resistor being selectively coupled between said first input control line and a voltage source; a second resistor being selectively coupled between said second input control line and said voltage source; a third resistor being selectively coupled between a second data out terminal and said voltage source; and an emulation bit whereby when said emulation bit is asserted, said first, second, and third resistors are decoupled from said first input control line, said second input control line, and said second data out terminal.

Claim 14

The configuration memory of claim 11 wherein said first, second and third resistors are contained within a common physical package with said memory array.

Claim 15

The configuration memory of claim 7 further comprising: an oscillator, said oscillator selectively providing said clock signal; and a bidirectional clock terminal, said bidirectional clock terminal being selectively driven by said oscillator when said configuration memory is in a first mode of operation and by an external clock signal in a second mode of operation.

Claim 16

The configuration memory of claim 7 further comprising: a second output terminal, said output terminal being changed from a first logic state to a second logic state responsive to receipt of a private JTAG instruction through said JTAG port.

Claim 17

An integrated circuit memory comprising: a memory array of memory cells; an address counter coupled to the memory array; an output terminal that outputs a logic state depending on the value of said address counter; a data output port coupled to the memory array to output information from the memory array; and a JTAG circuit to receive JTAG instructions from a JTAG port, wherein in response to one of the JTAG instructions, input data provided using the JTAG port is written into the memory array.

Claim 18

An integrated circuit memory comprising: a memory array of memory cells; an address counter coupled to the memory array; an output terminal that outputs a logic state depending on the value of said address counter; a data output port coupled to the memory array to output information from the memory array; and a JTAG circuit to receive JTAG instructions from a JTAG port, wherein in response to one of the JTAG instructions, input data provided using the JTAG port is written into the memory array.

Claim 19

The integrated circuit memory of claim 15 wherein the integrated circuit memory is a serial memory, and the input data is clocked serially into the integrated circuit memory.

Claim 20

The integrated circuit memory of claim 15 wherein the memory cells are flash cells.

Claim 21

The integrated circuit memory of claim 15 wherein the memory cells are EEPROM cells.

Claim 22

The integrated circuit memory of claim 15 wherein the memory cells are EPROM cells.

Claim 23

An integrated circuit memory comprising: a memory array with an address port; an address counter coupled to the address port of the memory array; a first output terminal coupled to the address counter, the first output terminal having a logic state based on a value of said address counter; a data out port coupled to the memory array to transfer data out of said integrated circuit memory; and JTAG circuitry to receive one of a group of JTAG instructions and controlling operation of said integrated circuit memory according to said JTAG instruction.

Claim 24

An integrated circuit memory comprising: a memory array with an address port; an address counter coupled to the address port of the memory array; a first output terminal coupled to the address counter, the first output terminal having a logic state based on a value of said address counter; a data out port coupled to the memory array to transfer data out of said integrated circuit memory; and JTAG circuitry to receive one of a group of JTAG instructions and controlling operation of said integrated circuit memory according to said JTAG instruction.

Claim 25

The integrated circuit memory of claim 20 further comprising: a decoder to cause the first output terminal to output a first logic state if the address counter equals a particular value.

Claim 26

The integrated circuit memory of claim 21 wherein the decoder outputs a second logic state if the address counter does not equal the particular value.

Claim 27

The integrated circuit memory of claim 21 wherein the particular value is the address location of a last item of information in the memory array.

Claim 28

The integrated circuit memory of claim 20 wherein said memory array is programmable via said JTAG port.

Claim 29

The integrated circuit memory of claim 23 wherein said information is configuration data for configuring programmable logic devices.

Claim 30

The configuration memory of claim 20 further comprising: a second output terminal coupled to said JTAG circuitry to change from a first logic state to a second logic state responsive to receipt of a private JTAG instruction through said JTAG port.

Claim 31

The configuration memory of claim 26 further comprising: a resistor coupled between said second output terminal and a voltage source; and and a programmable switch to selectively decouple said resistor from said data out port in response to an emulation bit.