US5734868A
Expired / Lapsed
US
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Efficient in-system programming structure and method for non-volatile programmable logic devices
Assignee: Xilinx Inc
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Filing: 1995-08-09
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Granted: 1998-03-31
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Expires: 2015-08-09
Abstract
Abstract An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.
Inventors
- 👤 Derek R. Curd
- 👤 Kameswara K. Rao
- 👤 Napoleon W. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/17704
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
86 words
An in-system programing/erasing/verifying structure for non-volatile programable logic devices including: a data input pin; a data output pin; an instruction register; a plurality of data registers including an ISP register, wherein said ISP register includes: an address field; a data field; and a status field, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin; and a controller for synchronizing the clocking of said instruction register and said plurality of data registers.
Claim 2
Dependent Claim
86 words
An in-system programing/erasing/verifying structure for non-volatile programable logic devices including: a data input pin; a data output pin; an instruction register; a plurality of data registers including an ISP register, wherein said ISP register includes: an address field; a data field; and a status field, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin; and a controller for synchronizing the clocking of said instruction register and said plurality of data registers.
Claim 3
Dependent Claim
15 words
The in-system programming/erasing/verifying structure in claim 1 wherein said status field stores a two-bit code.
Claim 4
Dependent Claim
63 words
An in-system programing method for a non-volatile programable logic device including: shifting a program instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating a programing pulse for said data at said address; terminating said programing pulse; and automatically performing a verify operation on said address.
Claim 5
Dependent Claim
63 words
An in-system programing method for a non-volatile programable logic device including: shifting a program instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating a programing pulse for said data at said address; terminating said programing pulse; and automatically performing a verify operation on said address.
Claim 6
Dependent Claim
19 words
The in-system programing method of claim 3 wherein said verify operation determines whether a selected memory cell is programmed.
Claim 7
Dependent Claim
28 words
The in-system programing method of claim 4 wherein said verify operation compares the state stored by said selected memory cell to said data shifted into said ISP register.
Claim 8
Dependent Claim
25 words
The in-system programming method of claim 5 wherein if said state matches said value, then a predetermined status code is loaded into said ISP register.
Claim 9
Dependent Claim
60 words
An in-system erasing method for a non-volatile programmable logic device including: shifting a erase instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating an erasing pulse at said address; terminating said erasing pulse; and automatically performing a verify operation on said address.
Claim 10
Dependent Claim
60 words
An in-system erasing method for a non-volatile programmable logic device including: shifting a erase instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating an erasing pulse at said address; terminating said erasing pulse; and automatically performing a verify operation on said address.
Claim 11
Dependent Claim
19 words
The in-system erasing method of claim 7 wherein said verify operation determines whether a selected memory cell is erased.
Claim 12
Dependent Claim
25 words
The in-system erasing method of claim 8 wherein if said memory cell is erased, then a predetermined status code is loaded into said ISP register.
Claim 13
Dependent Claim
71 words
An in-system verifying method for a non-volatile programmable logic device including: shifting a verify instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating a verifying pulse at said address; terminating said verifying pulse; and automatically loading the state of the memory cell at said address into a data field of said ISP register.
Claim 14
Dependent Claim
71 words
An in-system verifying method for a non-volatile programmable logic device including: shifting a verify instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating a verifying pulse at said address; terminating said verifying pulse; and automatically loading the state of the memory cell at said address into a data field of said ISP register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |