US5646901A
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CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors
Assignee: Lattice Semiconductor Corp
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Filing: 1996-03-26
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Granted: 1997-07-08
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Expires: 2016-03-26
Abstract
Abstract An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.
Inventors
- 👤 Bradley A. Sharpe-Geisler
- 👤 Jonathan Lin
- 👤 Radu Barsan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:05
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/045; H; H10; H10B; H10B69/00; G11C2216/00; G11C2216/02; G11C2216/10
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
110 words
A CMOS memory cell comprising: a common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; an output node; an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.
Claim 2
Dependent Claim
110 words
A CMOS memory cell comprising: a common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; an output node; an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.
Claim 3
Dependent Claim
15 words
The CMOS memory cell of claim 1, wherein the pass gate is an NMOS transistor.
Claim 4
Dependent Claim
21 words
The CMOS memory cell of claim 1, wherein the output node is further connected to the drain of the PMOS transistor.
Claim 5
Dependent Claim
22 words
The CMOS memory cell of claim 1, wherein the NMOS transistor is a depletion mode transistor having a threshold below zero volts.
Claim 6
Dependent Claim
94 words
A CMOS memory cell comprising: a common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; an output node; an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; a PMOS transistor having a drain connected to the drain of the NMOS transistor, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel.
Claim 7
Dependent Claim
94 words
A CMOS memory cell comprising: a common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; an output node; an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; a PMOS transistor having a drain connected to the drain of the NMOS transistor, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel.
Claim 8
Independent Claim
187 words
A method of programming a first CMOS memory cell including a common floating gate; a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate; an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein programming results in electrons being added to the common floating gate, programming comprising the steps of: applying a first voltage difference between the ACG node and the WCL node so that electrons transfer from the source of the NMOS transistor to the common floating gate; and applying a second voltage difference, concurrent with application of the first voltage difference, between the ACG node and the WCH node so that substantially no tunneling of electrons occurs from the source of the PMOS transistor to the common floating gate.
Claim 9
Independent Claim
187 words
A method of programming a first CMOS memory cell including a common floating gate; a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate; an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein programming results in electrons being added to the common floating gate, programming comprising the steps of: applying a first voltage difference between the ACG node and the WCL node so that electrons transfer from the source of the NMOS transistor to the common floating gate; and applying a second voltage difference, concurrent with application of the first voltage difference, between the ACG node and the WCH node so that substantially no tunneling of electrons occurs from the source of the PMOS transistor to the common floating gate.
Claim 10
Dependent Claim
106 words
The method of claim 6 further comprising a step for preventing current leakage in second CMOS memory cells having components similar to the first CMOS memory cell, with capacitors of the second CMOS memory cells having ACG nodes connected to the ACG node of the first CMOS memory cell, the further step comprising: applying a third voltage difference between the ACG node and the WCL node of the second memory cells, the third voltage difference being less than the first voltage difference so that substantially no electrons transfer from the source of the NMOS transistor to the common floating gate of the second CMOS memory cells.
Claim 11
Dependent Claim
41 words
The method of claim 7, wherein the third voltage difference is a minimum reliable voltage difference which will substantially prevent electrons from transferring from the source of the NMOS transistor to the common floating gate of the second CMOS memory cells.
Claim 12
Dependent Claim
87 words
The method of claim 7 further comprising a step for preventing current leakage in third CMOS memory cells having components similar to the first CMOS memory cell, with WCL lines of the third CMOS memory cells being connected to the WCL lines of the second CMOS memory cell, the further step comprising: applying a fourth voltage difference between the ACG line and the WCL node of the second memory cells, the fourth voltage difference having a value set to prevent tunneling in the third CMOS memory cells.
Claim 13
Dependent Claim
66 words
The method of claim 6, wherein the source and drain of the PMOS transistor is provided in an n well of a p- type substrate, the n well being connected to an Nwell node, the method further comprising the step of: applying a voltage potential to the Nwell node greater than a voltage potential provided to the WCH node during application of the second voltage difference.
Claim 14
Dependent Claim
130 words
The method of claim 9 further comprising steps for erasing the first, second and third CMOS memory cells, wherein erasing results in electrons being added to the common floating gate, the further steps comprising: applying a fifth voltage difference between the ACG node and the WCH node of the first, second and third CMOS memory cells so that electrons transfer from the common floating gate to the source of the PMOS transistor in each CMOS memory cell; and applying substantially no voltage difference between the WCL and WCH nodes of the first, second and third CMOS memory cells, concurrent with application of the fifth voltage difference, so that no substantial electron transfer occurs from the common floating gate to the source of the NMOS transistor in each CMOS memory cell.
Claim 15
Independent Claim
187 words
The method of erasing a CMOS memory cell including a common floating gate; a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate; an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein erasing results in electrons being added to the common floating gate, erasing comprising the steps of: applying a voltage difference between the ACG node and the WCH node of the CMOS memory cell so that electrons transfer from the common floating gate to the source of the PMOS transistor; and applying substantially no voltage difference between the WCL and WCH nodes concurrent with application of the fifth voltage difference, so that no substantial electron transfer occurs from the common floating gate to the source of the NMOS transistor.
Claim 16
Independent Claim
187 words
The method of erasing a CMOS memory cell including a common floating gate; a capacitor having a first terminal forming an ACG node and a second terminal coupled to the common floating gate; an NMOS transistor having a source connected to a WCL node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a PMOS transistor having a source connected to a WCH node, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel, wherein erasing results in electrons being added to the common floating gate, erasing comprising the steps of: applying a voltage difference between the ACG node and the WCH node of the CMOS memory cell so that electrons transfer from the common floating gate to the source of the PMOS transistor; and applying substantially no voltage difference between the WCL and WCH nodes concurrent with application of the fifth voltage difference, so that no substantial electron transfer occurs from the common floating gate to the source of the NMOS transistor.
Claim 17
Dependent Claim
139 words
A programmable logic device (PLD) receiving an input, the PLD comprising: a sense amplifier having a product term (PT) input and a product term ground (PTG) input; a plurality of memory cells, each comprising: a common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; an output node; an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.
Claim 18
Dependent Claim
139 words
A programmable logic device (PLD) receiving an input, the PLD comprising: a sense amplifier having a product term (PT) input and a product term ground (PTG) input; a plurality of memory cells, each comprising: a common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; an output node; an NMOS transistor having a drain, a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; a PMOS transistor having a channel formed between its source and drain, and a tunneling oxide region and the common floating gate overlying its channel; and a pass gate having a source to drain path coupling the drain of the NMOS transistor to the output node of the CMOS memory cell.
References Cited (Backward Citations)
US4885719A
Cited
US5440509A
Cited
US4858185A
Cited
US4829203A
Cited
US4862019A
Cited
US4866307A
Cited
US5170373A
Cited
US5404328A
Cited
US5272368A
Cited
US5270587A
Cited
US5148391A
Cited
US5555204A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |