Memory cell having floating gate and semiconductor memory using the same

Claim 2

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into said memory cell and outputting said data, said first field effect transistor having a first threshold voltage; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor and having a second threshold voltage; said first field effect transistor and said second field effect transistor having an operating voltage range in which both the first field effect transistor and said second field effect transistor are ON; said first threshold voltage being higher than the highest voltage of said operating voltage range and lower than said first voltage; said second threshold voltage being lower than the lowest voltage of said operating voltage range and higher than said second voltage; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistor, said data being stored in the floating gates of said first and second field effect transistors.

Claim 3

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into said memory cell and outputting said data; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the floating gates of said first and second field effect transistors; said first and second field effect transistors and said capacitor having, in common, a semiconductor substrate, an insulator film formed on said semiconductor substrate and a conduction layer; said first field effect transistors having a well region, formed in said semiconductor substrate and having a conduction type opposite to that of said semiconductor substrate, and source and drain regions being formed in said well region; said second field effect transistor having source and drain regions formed in said semiconductor substrate; said capacitor having an impurity diffused region formed in said semiconductor substrate and having a conduction type which is the same as that of said well region; and said conduction layer comprising a first portion located above said well region of said first field effect transistor and functioning as the floating gate of said first field effect transistor, a second portion located between the source and drain regions of said second field effect transistor and functioning as the floating gate of said second field effect transistor; and a third portion located above said impurity diffused region of said capacitor and serving as the first terminal of said capacitor.

Claim 4

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into said memory cell and outputting said data; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the floating gates of said first and second field effect transistors; said first and second field effect transistors and said capacitor having, in common, a semiconductor substrate, an insulator film formed on said semiconductor substrate and a conduction layer; said first field effect transistors having a well region, formed in said semiconductor substrate and having a conduction type opposite to that of said semiconductor substrate, and source and drain regions being formed in said well region; said second field effect transistor having source and drain regions formed in said semiconductor substrate; said capacitor having an impurity diffused region formed in said semiconductor substrate and having a conduction type which is the same as that of said well region; and said conduction layer comprising a first portion located above said well region of said first field effect transistor and functioning as the floating gate of said first field effect transistor, a second portion located between the source and drain regions of said second field effect transistor and functioning as the floating gate of said second field effect transistor; and a third portion located above said impurity diffused region of said capacitor and serving as the first terminal of said capacitor.

Claim 5

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into said memory cell and outputting said data; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the floating gates of said first and second field effect transistors; said first and second field effect transistors and said capacitor having, in common, a semiconductor substrate, a first insulator film formed on said semiconductor substrate, a first conduction layer formed on said first insulator film, a second insulator film formed on said first conduction layer, and a second conduction layer formed on said second insulator film; said first field effect transistor having a well region, formed in said semiconductor substrate and having a conduction type opposite to that of said semiconductor substrate, and source and drain regions formed in said well region; said second field effect transistor having source and drain regions formed in said semiconductor substrate; said first conduction layer functioning in common as the respective floating gates of said first and second field effect transistors as well as the second terminal of said capacitor; and said second insulator film functioning as the first terminal of said capacitor.

Claim 6

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving data to be written into said memory cell and outputting said data; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the floating gates of said first and second field effect transistors; said first and second field effect transistors and said capacitor having, in common, a semiconductor substrate, a first insulator film formed on said semiconductor substrate, a first conduction layer formed on said first insulator film, a second insulator film formed on said first conduction layer, and a second conduction layer formed on said second insulator film; said first field effect transistor having a well region, formed in said semiconductor substrate and having a conduction type opposite to that of said semiconductor substrate, and source and drain regions formed in said well region; said second field effect transistor having source and drain regions formed in said semiconductor substrate; said first conduction layer functioning in common as the respective floating gates of said first and second field effect transistors as well as the second terminal of said capacitor; and said second insulator film functioning as the first terminal of said capacitor.

Claim 7

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain outputting data stored in said memory cell; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a third field effect transistor having a drain receiving data to be written into said memory cell, a source receiving said second voltage, and a gate connected in common to the respective gates of said first and second field effect transistors; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors and the gate of said third field effect transistor, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 8

A memory cell for storing data comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain outputting data stored in said memory cell; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a third field effect transistor having a drain receiving data to be written into said memory cell, a source receiving said second voltage, and a gate connected in common to the respective gates of said first and second field effect transistors; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors and the gate of said third field effect transistor, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 9

A memory cell as claimed in claim 4, wherein: said first field effect transistor has a first threshold voltage; said second field effect transistor has a second threshold voltage; said first field effect transistor and said second field effect transistor have an operating voltage range in which both the first field effect transistor and said second field effect transistor are ON; said first threshold voltage is higher than the highest voltage of said operating voltage range and lower than said first voltage; and said second threshold voltage is lower than the lowest voltage of said operating voltage range and higher than said second voltage.

Claim 10

A semiconductor memory comprising: a data input terminal; a memory cell; write amplifier means for writing data applied to said data input terminal into said memory cell; and a data output terminal, said memory cell comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving the data from said write amplifier means and outputting said data to said data output terminal; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 11

A semiconductor memory comprising: a data input terminal; a memory cell; write amplifier means for writing data applied to said data input terminal into said memory cell; and a data output terminal, said memory cell comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving the data from said write amplifier means and outputting said data to said data output terminal; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 12

A semiconductor memory as claimed in claim 6, further comprising voltage generating means for generating said first voltage, wherein: said first field effect transistor has a first threshold voltage; said second field effect transistor has a second threshold voltage; and said first voltage is lower than the sum total of said first threshold voltage and said second threshold voltage.

Claim 13

A semiconductor memory as claimed in claim 7, further comprising sense amplifier means, coupled between said output terminal and the respective drains of said first and second field effect transistors, for receiving and amplifying said data output at the commonly connected, respective drains of said first and second field effect transistors.

Claim 14

A semiconductor memory comprising: a data input terminal; a memory cell; write amplifier means for writing data applied to said data input terminal into said memory cell; and a data output terminal, said memory cell comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving the data from said write amplifier means and outputting said data to said data output terminal, said first field effect transistor having a first threshold voltage, a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor said second field effect transistor having a second threshold voltage, said first field effect transistor and said second field effect transistor having an operation voltage range in which both the first field effect transistor and said second field effect transistor are ON, said first threshold voltage being higher than a highest voltage of said operation voltage range and lower than said first voltage and said second threshold voltage being lower than a lowest voltage of said operation voltage range and higher than said second voltage, and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 15

A semiconductor memory comprising: a data input terminal; a memory cell; write amplifier means for writing data applied to said data input terminal into said memory cell; and a data output terminal, said memory cell comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain receiving the data from said write amplifier means and outputting said data to said data output terminal, said first field effect transistor having a first threshold voltage, a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor said second field effect transistor having a second threshold voltage, said first field effect transistor and said second field effect transistor having an operation voltage range in which both the first field effect transistor and said second field effect transistor are ON, said first threshold voltage being higher than a highest voltage of said operation voltage range and lower than said first voltage and said second threshold voltage being lower than a lowest voltage of said operation voltage range and higher than said second voltage, and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 16

A semiconductor memory comprising: a data input terminal; a memory cell; write amplifier means for writing data applied to said data input terminal into said memory cell; and a data output terminal directly receiving data read out from said memory cell, said memory cell comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain directly outputting the data stored in said memory cell to said data output terminal; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a third field effect transistor having a drain receiving the data from said write amplifier means, a source receiving said second voltage, and a gate connected to the respective gates of said first and second field effect transistors; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors and the gate of said third field effect transistor, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 17

A semiconductor memory comprising: a data input terminal; a memory cell; write amplifier means for writing data applied to said data input terminal into said memory cell; and a data output terminal directly receiving data read out from said memory cell, said memory cell comprising: a first field effect transistor having a source receiving a first voltage, a floating gate, and a drain directly outputting the data stored in said memory cell to said data output terminal; a second field effect transistor having a source receiving a second voltage, a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor, said second field effect transistor having a conduction type opposite to that of said first field effect transistor; a third field effect transistor having a drain receiving the data from said write amplifier means, a source receiving said second voltage, and a gate connected to the respective gates of said first and second field effect transistors; and a capacitor having a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected in common to the respective floating gates of said first and second field effect transistors and the gate of said third field effect transistor, said data being stored in the respective floating gates of said first and second field effect transistors.

Claim 18

A memory cell as claimed in claim 10, wherein: said first field effect transistor has a first threshold voltage; said second field effect transistor has a second threshold voltage; said first field effect transistor and said second field effect transistor have an operating voltage range in which both the first field effect transistor and said second field effect transistor are ON; said first threshold voltage is higher than the highest voltage of said operating voltage range and lower than said first voltage; and said second threshold voltage is lower than the lowest voltage of said operating voltage range and higher than said second voltage.