Complementary semiconductor memory device with pull-up and pull down

Claim 2

A master slice type semiconductor memory device, comprising: a plurality of basic cells, each constituted by p- and n-channel MOS transistors, formed as a gate array on a CMOS master slice chip; first and second power terminals; a plurality of word lines; a plurality of bit lines; and a memory section including a plurality of said p- and n-channel MOS transistors, each of said MOS transistors having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source selectively connected to one of said first and second power terminals to form a memory cell which is driven via the corresponding word line and supplies a potential of said one power terminal to the corresponding bit line as preset data, in which said plurality of bit lines includes a first bit line dedicated to connection with the n-channel MOS transistors and a second bit line dedicated to connection with the p-channel MOS transistors, the memory device further comprising a pull-up compensation circuit for pulling up an output potential of said first bit line and a pull-down compensation circuit for pulling down an output potential of said second bit line.

Claim 3

A master slice type semiconductor memory device comprising: a plurality of basic cells, each constituted by p- and n-channel MOS transistors, formed as a gate array on a CMOS master slice chip; first and second power terminals; a plurality of word lines; a plurality of bit lines, including a first bit line dedicated to connection with the n-channel MOS transistors and a second bit line dedicated to connection with the p-channel MOS transistors; a memory section including a plurality of said p- and n-channel MOS transistors, each of said MOS transistors having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source selectively connected to one of said first and second power terminals to form a memory cell which is driven via the corresponding word line and supplies a potential of said one power terminal to the corresponding bit line as preset data; a pull-up compensation circuit for pulling up an output potential of said first bit line, wherein said pull-up compensation circuit includes a first inverter connected to receive the output potential of the first bit line, and at least one p-channel MOS transistor having a gate connected to an output terminal of said first inverter and a current path connected in series between said first bit line and said first power terminal; and a pull-down compensation circuit for pulling down an output potential of said second bit line, wherein said pull-down compensation circuits includes a second inverter connected to receive the output potential of the second bit line, and at least one n-channel MOS transistor having a gate connected to an output terminal of said second inverter and a current path connected in series between said second bit line and said second power terminal.

Claim 4

A master slice type semiconductor memory device comprising: a plurality of basic cells, each constituted by p- and n-channel MOS transistors, formed as a gate array on a CMOS master slice chip; first and second power terminals; a plurality of word lines; a plurality of bit lines, including a first bit line dedicated to connection with the n-channel MOS transistors and a second bit line dedicated to connection with the p-channel MOS transistors; a memory section including a plurality of said p- and n-channel MOS transistors, each of said MOS transistors having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source selectively connected to one of said first and second power terminals to form a memory cell which is driven via the corresponding word line and supplies a potential of said one power terminal to the corresponding bit line as preset data; a pull-up compensation circuit for pulling up an output potential of said first bit line, wherein said pull-up compensation circuit includes a first inverter connected to receive the output potential of the first bit line, and at least one p-channel MOS transistor having a gate connected to an output terminal of said first inverter and a current path connected in series between said first bit line and said first power terminal; and a pull-down compensation circuit for pulling down an output potential of said second bit line, wherein said pull-down compensation circuits includes a second inverter connected to receive the output potential of the second bit line, and at least one n-channel MOS transistor having a gate connected to an output terminal of said second inverter and a current path connected in series between said second bit line and said second power terminal.

Claim 5

A master slice type semiconductor memory device according to claim 2, wherein the operation point of said pull-up compensation circuit is determined by the number of said MOS transistors connected between said first bit line and said first power terminal, and the operation point of said pull-down compensation circuit is determined by the number of said MOS transistors connected between said second bit line and said second power terminal.

Claim 6

A master slice type semiconductor memory device according to claim 2, wherein the operation point of said pull-up compensation circuit is determined by the threshold voltage of said first inverter, and the operation point of said pull-down compensation circuit is determined by the threshold voltage of said second inverter.