High-speed mos sense amplifier

Claim 1

A sense amplifier, comprising: a first source of potential and a second source of potential; an input terminal and an output terminal; means for developing a reference potential including, a first FET having a first gate, a first source, and a first drain coupled to said first source of potential, and a second FET having a second gate, a second source coupled to said second source of potential, and a second drain coupled to said first source; a differential amplifier responsive to an input signal applied to said input terminal and operative to develop an output signal at said output terminal, and including, a third FET having a third gate coupled to said input terminal, a third source coupled to said second source of potential, and a third drain coupled to said first source of potential, and a fourth FET having a fourth gate coupled to said second drain for receiving said reference potential, a fourth drain coupled to said first source of potential, and a fourth source coupled to said third source; voltage-dividing means normally biasing said input terminal to a quiesent potential, said voltage-dividing means including, a first impedance coupled between said first source of potential and said input terminal, and a second impedance coupled between said input terminal and said second source of potential; first signal-limiting means responsive to said output signal and operative to prevent said input signal from becoming more positive than a first predetermined potential; and second signal-limiting means responsive to said output signal and operative to prevent said input signal from becoming more negative than a second predetermined potential.