US6509639B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three-dimensional stacked semiconductor package
Assignee: Individual
•
Filing: 2002-04-30
•
Granted: 2003-01-21
•
Expires: 2022-04-30
Abstract
Abstract A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.
Inventors
- 👤 Charles W. C. Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:43
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/20; H10W90/22; H10W90/291; H10W90/297; H10W90/701; H10W90/721
Claims Analysis
Total Claims: 321
Claim 1
Independent Claim
314 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip and does not extend to the second surface of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip and does not extend to the second surface of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is between the first and second surfaces of the second chip.
Claim 2
Dependent Claim
314 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip and does not extend to the second surface of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip and does not extend to the second surface of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is between the first and second surfaces of the second chip.
Claim 3
Dependent Claim
37 words
The semiconductor package of claim 1 , wherein the first conductive trace consists of the first routing line and the first pillar, and the second conductive trace consists of the second routing line and the second pillar.
Claim 4
Dependent Claim
29 words
The semiconductor package of claim 2 , wherein the first conductive trace is a single continuous metal lead, and the second conductive trace is a single continuous metal lead.
Claim 5
Dependent Claim
25 words
The semiconductor package of claim 3 , wherein the first routing line overlaps the first pad, and the second routing line overlaps the second pad.
Claim 6
Dependent Claim
37 words
The semiconductor package of claim 3 , wherein the first pillar is disposed at a distal end of the first routing line, and the second pillar is disposed at a distal end of the second routing line.
Claim 7
Dependent Claim
20 words
The semiconductor package of claim 1 , wherein the first and second conductive traces have essentially identical shapes and sizes.
Claim 8
Dependent Claim
135 words
The semiconductor package of claim 1 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and overlaps the first pad, the second routing line is essentially flat and coplanar with the first surface of the second chip and overlaps the second pad, the first pillar is disposed at a distal end of the first routing line, the second pillar is disposed at a distal end of the second routing line, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 9
Dependent Claim
24 words
The semiconductor package of claim 1 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip.
Claim 10
Dependent Claim
22 words
The semiconductor package of claim 8 , wherein the second conductive trace includes another pillar within the periphery of the second chip.
Claim 11
Dependent Claim
43 words
The semiconductor package of claim 1 , wherein the first routing line is essentially flat and parallel to the first surface of the first chip, and the second routing line is essentially flat and parallel to the first surface of the second chip.
Claim 12
Dependent Claim
39 words
The semiconductor package of claim 10 , wherein the first routing line is essentially coplanar with the first surface of the first chip, and the second routing line is essentially coplanar with the first surface of the second chip.
Claim 13
Dependent Claim
29 words
The semiconductor package of claim 11 , wherein the first routing line is contiguous with the first pillar, and the second routing line is contiguous with the second pillar.
Claim 14
Dependent Claim
25 words
The semiconductor package of claim 12 , wherein the first routing line overlaps the first pad, and the second routing line overlaps the second pad.
Claim 15
Dependent Claim
20 words
The semiconductor package of claim 1 , wherein the first routing line contacts the second surface of the second chip.
Claim 16
Dependent Claim
24 words
The semiconductor package of claim 1 , wherein the first routing line contacts an adhesive that contacts the second surface of the second chip.
Claim 17
Dependent Claim
45 words
The semiconductor package of claim 1 , wherein the second surface of the first pillar is essentially parallel to the first surface of the first chip, and the second surface of the second pillar is essentially parallel to the first surface of the second chip.
Claim 18
Dependent Claim
45 words
The semiconductor package of claim 16 , wherein the second surface of the first pillar is essentially coplanar with the first surface of the first chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip.
Claim 19
Dependent Claim
39 words
The semiconductor package of claim 1 , wherein the first pillar extends orthogonally to the first and second surfaces of the first chip, and the second pillar extends orthogonally to the first and second surfaces of the second chip.
Claim 20
Dependent Claim
47 words
The semiconductor package of claim 1 , wherein the first and second surfaces of the first pillar are separated by a first distance, the first and second surfaces of the second chip are separated by a second distance, and the first and second distances are essentially identical.
Claim 21
Dependent Claim
37 words
The semiconductor package of claim 1 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 22
Dependent Claim
26 words
The semiconductor package of claim 1 , wherein the first surface of the first pillar is essentially parallel to the second surface of the second pillar.
Claim 23
Dependent Claim
26 words
The semiconductor package of claim 1 , wherein the first surface of the first pillar does not extend past the second surface of the second pillar.
Claim 24
Dependent Claim
53 words
The semiconductor package of claim 1 , wherein the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, and the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar.
Claim 25
Dependent Claim
30 words
The semiconductor package of claim 1 , wherein the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar.
Claim 26
Dependent Claim
23 words
The semiconductor package of claim 1 , wherein the first surface of the first pillar contacts the second surface of the second pillar.
Claim 27
Dependent Claim
49 words
The semiconductor package of claim 1 , wherein the first surface of the first pillar is separated from the second surface of the second pillar, and the conductive bond contacts and is sandwiched between the first surface of the first pillar and the second surface of the second pillar.
Claim 28
Dependent Claim
37 words
The semiconductor package of claim 1 , wherein the first pillar is disposed at a distal end of the first routing line, and the second pillar is disposed at a distal end of the second routing line.
Claim 29
Dependent Claim
49 words
The semiconductor package of claim 1 , wherein the first pillar has a conical shape in which its diameter increases from its first surface to its second surface, and the second pillar has a conical shape in which its diameter increases from its first surface to its second surface.
Claim 30
Dependent Claim
41 words
The semiconductor package of claim 1 , wherein the first pillar has a smaller diameter at its first surface than at its second surface, and the second pillar has a smaller diameter at its first surface than at its second surface.
Claim 31
Dependent Claim
22 words
The semiconductor package of claim 1 , wherein the conductive bond is disposed outside the peripheries of the first and second chips.
Claim 32
Dependent Claim
22 words
The semiconductor package of claim 1 , wherein the conductive bond is the only material that contacts the first and second pillars.
Claim 33
Dependent Claim
27 words
The semiconductor package of claim 1 , wherein the conductive bond is the only material that mechanically attaches the first and second conductive traces to one another.
Claim 34
Dependent Claim
33 words
The semiconductor package of claim 1 , wherein the conductive bond and the first and second conductive traces are the only materials in an electrically conductive path between the first and second pads.
Claim 35
Dependent Claim
32 words
The semiconductor package of claim 1 , wherein the conductive bond is selected from the group consisting of solder, conductive adhesive, conductive paste, electroplated metal, electrolessly plated metal, and a welded joint.
Claim 36
Dependent Claim
55 words
The semiconductor package of claim 1 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 37
Dependent Claim
22 words
The semiconductor package of claim 1 , wherein the first semiconductor chip assembly is essentially identical to the second semiconductor chip assembly.
Claim 38
Dependent Claim
33 words
The semiconductor package of claim 1 , wherein the first surface of the first chip and the second surface of the second chip are separated from one another by at most 30 microns.
Claim 39
Dependent Claim
19 words
The semiconductor package of claim 1 , including a single continuous encapsulant that contacts the first and second chips.
Claim 40
Dependent Claim
195 words
The semiconductor package of claim 1 , including: a third semiconductor chip assembly that includes a third semiconductor chip and a third conductive trace, wherein the third chip includes first and second opposing surfaces, the first surface of the third chip includes a third conductive pad, the third conductive trace includes a third routing line and a third pillar, the third routing line extends within and outside a periphery of the third chip and is electrically connected to the third pad, the third pillar includes first and second opposing surfaces and is disposed outside the periphery of the third chip and does not extend to the second surface of the third chip, and the first surface of the third pillar faces away from the first surface of the third chip; and a second conductive bond that contacts and electrically connects the second and third pillars; wherein the first surface of the second chip faces the second surface of the third chip, the first surface of the second pillar faces the second surface of the third pillar, and the first surface of the second pillar is between the first and second surfaces of the third chip.
Claim 41
Dependent Claim
18 words
The semiconductor package of claim 1 , wherein the package is devoid of wire bonds and TAB leads.
Claim 42
Dependent Claim
421 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; and a conductive bond disposed outside the peripheries of the first and second chips that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, the first surface of the first pillar is between the first and second surfaces of the second chip, and the first and second pillars have essentially identical shapes and sizes.
Claim 43
Dependent Claim
421 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; and a conductive bond disposed outside the peripheries of the first and second chips that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, the first surface of the first pillar is between the first and second surfaces of the second chip, and the first and second pillars have essentially identical shapes and sizes.
Claim 44
Dependent Claim
51 words
The semiconductor package of claim 41 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, and the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar.
Claim 45
Dependent Claim
39 words
The semiconductor package of claim 41 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 46
Dependent Claim
20 words
The semiconductor package of claim 41 , wherein the first routing line contacts the second surface of the second chip.
Claim 47
Dependent Claim
37 words
The semiconductor package of claim 41 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 48
Dependent Claim
26 words
The semiconductor package of claim 41 , wherein the first surface of the first pillar does not extend past the second surface of the second pillar.
Claim 49
Dependent Claim
107 words
The semiconductor package of claim 41 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar, and the first surface of the first pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 50
Dependent Claim
55 words
The semiconductor package of claim 41 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 51
Dependent Claim
35 words
The semiconductor package of claim 41 , wherein the first semiconductor chip assembly is devoid of wire bonds and TAB leads, and the second semiconductor chip assembly is devoid of wire bonds and TAB leads.
Claim 52
Dependent Claim
260 words
The semiconductor package of claim 41 , including: a third semiconductor chip assembly that includes a third semiconductor chip and a third conductive trace, wherein the third chip includes first and second opposing surfaces, the first surface of the third chip includes a third conductive pad, the third conductive trace includes a third routing line and a third pillar, the third routing line is essentially flat and coplanar with the first surface of the third chip and extends within and outside a periphery of the third chip and overlaps and is electrically connected to the third pad, the third pillar includes first and second opposing surfaces and is disposed outside the periphery of the third chip at a distal end of the third routing line and does not extend to the second surface of the third chip, the first surface of the third pillar faces away from the first surface of the third chip, and the second surface of the third pillar is essentially coplanar with the first surface of the third chip; and a second conductive bond disposed outside the peripheries of the second and third chips that contacts and electrically connects the second and third pillars; wherein the first surface of the second chip faces the second surface of the third chip, the first surface of the second pillar faces the second surface of the third pillar, the first surface of the second pillar is between the first and second surfaces of the third chip, and the second and third conductive traces have essentially identical shapes and sizes.
Claim 53
Dependent Claim
258 words
A three-dimensional stacked semiconductor package, comprising: a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar faces away from the first surface of the chip; and a plurality of conductive bonds disposed outside the peripheries of the chips that each contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies; wherein for each of the assemblies, the chip is aligned with other chips in the package, and the pillars are aligned with other pillars in the package; and wherein for each of the assemblies above a lowest assembly in the package, the first surfaces of the pillars face the second surfaces of the pillars on the adjacent lower assembly, and the first surfaces of the pillars are between the first and second surfaces of the chip on the adjacent lower assembly.
Claim 54
Dependent Claim
258 words
A three-dimensional stacked semiconductor package, comprising: a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar faces away from the first surface of the chip; and a plurality of conductive bonds disposed outside the peripheries of the chips that each contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies; wherein for each of the assemblies, the chip is aligned with other chips in the package, and the pillars are aligned with other pillars in the package; and wherein for each of the assemblies above a lowest assembly in the package, the first surfaces of the pillars face the second surfaces of the pillars on the adjacent lower assembly, and the first surfaces of the pillars are between the first and second surfaces of the chip on the adjacent lower assembly.
Claim 55
Dependent Claim
88 words
The semiconductor package of claim 51 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 56
Dependent Claim
27 words
The semiconductor package of claim 51 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 57
Dependent Claim
32 words
The semiconductor package of claim 51 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 58
Dependent Claim
38 words
The semiconductor package of claim 51 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 59
Dependent Claim
58 words
The semiconductor package of claim 51 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 60
Dependent Claim
74 words
The semiconductor package of claim 51 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 61
Dependent Claim
28 words
The semiconductor package of claim 51 , including a single continuous encapsulant that contacts each of the routing lines, each of the pillars and each of the chips.
Claim 62
Dependent Claim
18 words
The semiconductor package of claim 51 , wherein each of the assemblies is essentially identical to one another.
Claim 63
Dependent Claim
18 words
The semiconductor package of claim 51 , wherein the package is devoid of wire bonds and TAB leads.
Claim 64
Independent Claim
390 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then moving the first and second assemblies towards one another while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars, wherein the first surface of the first pillar is between the first and second surfaces of the second chip.
Claim 65
Independent Claim
390 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then moving the first and second assemblies towards one another while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars, wherein the first surface of the first pillar is between the first and second surfaces of the second chip.
Claim 66
Dependent Claim
134 words
The method of claim 61 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and overlaps the first pad, the second routing line is essentially flat and coplanar with the first surface of the second chip and overlaps the second pad, the first pillar is disposed at a distal end of the first routing line, the second pillar is disposed at a distal end of the second routing line, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 67
Dependent Claim
38 words
The method of claim 61 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 68
Dependent Claim
25 words
The method of claim 61 , wherein the first assembly contacts the second surface of the second chip after moving the assemblies towards one another.
Claim 69
Dependent Claim
38 words
The method of claim 61 , wherein the first surface of the first pillar is closer to the first surface of the second chip than to the second surface of the second chip after solidifying the bonding material.
Claim 70
Dependent Claim
41 words
The method of claim 61 , wherein the first pillar does not extend to the second surface of the first chip, and the second pillar does not extend to the second surface of the second chip after solidifying the bonding material.
Claim 71
Dependent Claim
113 words
The method of claim 61 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar, and after positioning the first and second assemblies, the first surface of the first pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 72
Dependent Claim
19 words
The method of claim 61 , wherein the bonding material is solder paste and the conductive bond is solder.
Claim 73
Dependent Claim
33 words
The method of claim 61 , including forming an encapsulant on the first and second routing lines, the first and second pillars and the first and second chips after solidifying the bonding material.
Claim 74
Dependent Claim
17 words
The method of claim 61 , wherein the package is devoid of wire bonds and TAB leads.
Claim 75
Independent Claim
523 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; p 1 providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then applying pressure while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms until the first assembly contacts the second surface of the second chip, at which time the first surface of the first pillar is between the first and second surfaces of the second chip and separated from the second surface of the second pillar by the bonding material; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 76
Independent Claim
523 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; p 1 providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then applying pressure while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms until the first assembly contacts the second surface of the second chip, at which time the first surface of the first pillar is between the first and second surfaces of the second chip and separated from the second surface of the second pillar by the bonding material; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 77
Dependent Claim
62 words
The method of claim 71 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 78
Dependent Claim
38 words
The method of claim 71 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 79
Dependent Claim
23 words
The method of claim 71 , wherein the first routing line contacts the second surface of the second chip after applying the pressure.
Claim 80
Dependent Claim
36 words
The method of claim 71 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 81
Dependent Claim
110 words
The method of claim 71 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar, and after positioning the assemblies, the first surface of the first pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 82
Dependent Claim
54 words
The method of claim 71 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 83
Dependent Claim
45 words
The method of claim 71 , wherein the bonding material is solder paste, the conductive bond is solder, and solidifying the bonding material to form the conductive bond includes applying heat to reflow solder particles in the solder paste without applying pressure to the package.
Claim 84
Dependent Claim
33 words
The method of claim 71 , including forming an encapsulant on the first and second routing lines, the first and second pillars and the first and second chips after solidifying the bonding material.
Claim 85
Dependent Claim
17 words
The method of claim 71 , wherein the package is devoid of wire bonds and TAB leads.
Claim 86
Independent Claim
257 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar faces away from the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip.
Claim 87
Independent Claim
257 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar faces away from the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip.
Claim 88
Dependent Claim
87 words
The method of claim 81 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 89
Dependent Claim
26 words
The method of claim 81 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 90
Dependent Claim
31 words
The method of claim 81 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 91
Dependent Claim
37 words
The method of claim 81 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 92
Dependent Claim
57 words
The method of claim 81 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 93
Dependent Claim
73 words
The method of claim 81 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 94
Dependent Claim
30 words
The method of claim 81 , including forming an encapsulant that contacts each of the routing lines, each of the pillars and each of the chips after stacking the assemblies.
Claim 95
Dependent Claim
17 words
The method of claim 81 , wherein each of the assemblies is essentially identical to one another.
Claim 96
Dependent Claim
17 words
The method of claim 81 , wherein the package is devoid of wire bonds and TAB leads.
Claim 97
Independent Claim
263 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a single semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar is essentially parallel to and faces away from the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip.
Claim 98
Independent Claim
263 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a single semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar is essentially parallel to and faces away from the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip.
Claim 99
Dependent Claim
87 words
The method of claim 91 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 100
Dependent Claim
26 words
The method of claim 91 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 101
Dependent Claim
31 words
The method of claim 91 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 102
Dependent Claim
37 words
The method of claim 91 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 103
Dependent Claim
57 words
The method of claim 91 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 104
Dependent Claim
73 words
The method of claim 91 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 105
Dependent Claim
30 words
The method of claim 91 , including forming an encapsulant that contacts each of the routing lines, each of the pillars and each of the chips after stacking the assemblies.
Claim 106
Dependent Claim
17 words
The method of claim 91 , wherein each of the assemblies is essentially identical to one another.
Claim 107
Dependent Claim
17 words
The method of claim 91 , wherein the package is devoid of wire bonds and TAB leads.
Claim 108
Dependent Claim
318 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip and does not extend to the second surface of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, he first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip and does not extend to the second surface of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar.
Claim 109
Dependent Claim
318 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip and does not extend to the second surface of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, he first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip and does not extend to the second surface of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar.
Claim 110
Dependent Claim
37 words
The semiconductor package of claim 101 , wherein the first conductive trace consists of the first routing line and the first pillar, and the second conductive trace consists of the second routing line and the second pillar.
Claim 111
Dependent Claim
29 words
The semiconductor package of claim 102 , wherein the first conductive trace is a single continuous metal lead, and the second conductive trace is a single continuous metal lead.
Claim 112
Dependent Claim
25 words
The semiconductor package of claim 103 , wherein the first routing line overlaps the first pad, and the second routing line overlaps the second pad.
Claim 113
Dependent Claim
37 words
The semiconductor package of claim 103 , wherein the first pillar is disposed at a distal end of the first routing line, and the second pillar is disposed at a distal end of the second routing line.
Claim 114
Dependent Claim
20 words
The semiconductor package of claim 101 , wherein the first and second conductive traces have essentially identical shapes and sizes.
Claim 115
Dependent Claim
135 words
The semiconductor package of claim 101 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and overlaps the first pad, the second routing line is essentially flat and coplanar with the first surface of the second chip and overlaps the second pad, the first pillar is disposed at a distal end of the first routing line, the second pillar is disposed at a distal end of the second routing line, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 116
Dependent Claim
24 words
The semiconductor package of claim 101 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip.
Claim 117
Dependent Claim
22 words
The semiconductor package of claim 108 , wherein the second conductive trace includes another pillar within the periphery of the second chip.
Claim 118
Dependent Claim
43 words
The semiconductor package of claim 101 , wherein the first routing line is essentially flat and parallel to the first surface of the first chip, and the second routing line is essentially flat and parallel to the first surface of the second chip.
Claim 119
Dependent Claim
39 words
The semiconductor package of claim 110 , wherein the first routing line is essentially coplanar with the first surface of the first chip, and the second routing line is essentially coplanar with the first surface of the second chip.
Claim 120
Dependent Claim
29 words
The semiconductor package of claim 111 , wherein the first routing line is contiguous with the first pillar, and the second routing line is contiguous with the second pillar.
Claim 121
Dependent Claim
25 words
The semiconductor package of claim 112 , wherein the first routing line overlaps the first pad, and the second routing line overlaps the second pad.
Claim 122
Dependent Claim
20 words
The semiconductor package of claim 101 , wherein the first routing line contacts the second surface of the second chip.
Claim 123
Dependent Claim
24 words
The semiconductor package of claim 101 , wherein the first routing line contacts an adhesive that contacts the second surface of the second chip.
Claim 124
Dependent Claim
45 words
The semiconductor package of claim 101 , wherein the second surface of the first pillar is essentially parallel to the first surface of the first chip, and the second surface of the second pillar is essentially parallel to the first surface of the second chip.
Claim 125
Dependent Claim
45 words
The semiconductor package of claim 116 , wherein the second surface of the first pillar is essentially coplanar with the first surface of the first chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip.
Claim 126
Dependent Claim
39 words
The semiconductor package of claim 101 , wherein the first pillar extends orthogonally to the first and second surfaces of the first chip, and the second pillar extends orthogonally to the first and second surfaces of the second chip.
Claim 127
Dependent Claim
47 words
The semiconductor package of claim 101 , wherein the first and second surfaces of the first pillar are separated by a first distance, the first and second surfaces of the second chip are separated by a second distance, and the first and second distances are essentially identical.
Claim 128
Dependent Claim
37 words
The semiconductor package of claim 101 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 129
Dependent Claim
26 words
The semiconductor package of claim 101 , wherein the first surface of the first pillar is essentially parallel to the second surface of the second pillar.
Claim 130
Dependent Claim
26 words
The semiconductor package of claim 101 , wherein the first surface of the first pillar does not extend past the second surface of the second pillar.
Claim 131
Dependent Claim
53 words
The semiconductor package of claim 101 , wherein the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, and the first surface of the second pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 132
Dependent Claim
31 words
The semiconductor package of claim 101 , wherein the first and second surfaces of the first and second chips and the first and second pillars are essentially parallel to one another.
Claim 133
Dependent Claim
23 words
The semiconductor package of claim 101 , wherein the first surface of the first pillar contacts the second surface of the second pillar.
Claim 134
Dependent Claim
49 words
The semiconductor package of claim 101 , wherein the first surface of the first pillar is separated from the second surface of the second pillar, and the conductive bond contacts and is sandwiched between the first surface of the first pillar and the second surface of the second pillar.
Claim 135
Dependent Claim
37 words
The semiconductor package of claim 101 , wherein the first pillar is disposed at a distal end of the first routing line, and the second pillar is disposed at a distal end of the second routing line.
Claim 136
Dependent Claim
49 words
The semiconductor package of claim 101 , wherein the first pillar has a conical shape in which its diameter increases from its first surface to its second surface, and the second pillar has a conical shape in which its diameter increases from its first surface to its second surface.
Claim 137
Dependent Claim
41 words
The semiconductor package of claim 101 , wherein the first pillar has a smaller diameter at its first surface than at its second surface, and the second pillar has a smaller diameter at its first surface than at its second surface.
Claim 138
Dependent Claim
22 words
The semiconductor package of claim 101 , wherein the conductive bond is disposed outside the peripheries of the first and second chips.
Claim 139
Dependent Claim
22 words
The semiconductor package of claim 101 , wherein the conductive bond is the only material that contacts the first and second pillars.
Claim 140
Dependent Claim
27 words
The semiconductor package of claim 101 , wherein the conductive bond is the only material that mechanically attaches the first and second conductive traces to one another.
Claim 141
Dependent Claim
33 words
The semiconductor package of claim 101 , wherein the conductive bond and the first and second conductive traces are the only materials in an electrically conductive path between the first and second pads.
Claim 142
Dependent Claim
32 words
The semiconductor package of claim 101 , wherein the conductive bond is selected from the group consisting of solder, conductive adhesive, conductive paste, electroplated metal, electrolessly plated metal, and a welded joint.
Claim 143
Dependent Claim
55 words
The semiconductor package of claim 101 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 144
Dependent Claim
22 words
The semiconductor package of claim 101 , wherein the first semiconductor chip assembly is essentially identical to the second semiconductor chip assembly.
Claim 145
Dependent Claim
33 words
The semiconductor package of claim 101 , wherein the first surface of the first chip and the second surface of the second chip are separated from one another by at most 30 microns.
Claim 146
Dependent Claim
19 words
The semiconductor package of claim 101 , including a single continuous encapsulant that contacts the first and second chips.
Claim 147
Dependent Claim
199 words
The semiconductor package of claim 101 , including: a third semiconductor chip assembly that includes a third semiconductor chip and a third conductive trace, wherein the third chip includes first and second opposing surfaces, the first surface of the third chip includes a third conductive pad, the third conductive trace includes a third routing line and a third pillar, the third routing line extends within and outside a periphery of the third chip and is electrically connected to the third pad, the third pillar includes first and second opposing surfaces and is disposed outside the periphery of the third chip and does not extend to the second surface of the third chip, and the first surface of the third pillar faces away from the first surface of the third chip; and a second conductive bond that contacts and electrically connects the second and third pillars; wherein the first surface of the second chip faces the second surface of the third chip, the first surface of the second pillar faces the second surface of the third pillar, and the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the third pillar.
Claim 148
Dependent Claim
18 words
The semiconductor package of claim 101 , wherein the package is devoid of wire bonds and TAB leads.
Claim 149
Dependent Claim
425 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; and a conductive bond disposed outside the peripheries of the first and second chips that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar, and the first and second pillars have essentially identical shapes and sizes.
Claim 150
Dependent Claim
425 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; and a conductive bond disposed outside the peripheries of the first and second chips that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar, and the first and second pillars have essentially identical shapes and sizes.
Claim 151
Dependent Claim
51 words
The semiconductor package of claim 141 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, and the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar.
Claim 152
Dependent Claim
39 words
The semiconductor package of claim 141 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 153
Dependent Claim
20 words
The semiconductor package of claim 141 , wherein the first routing line contacts the second surface of the second chip.
Claim 154
Dependent Claim
37 words
The semiconductor package of claim 141 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 155
Dependent Claim
26 words
The semiconductor package of claim 141 , wherein the first surface of the first pillar does not extend past the second surface of the second pillar.
Claim 156
Dependent Claim
85 words
The semiconductor package of claim 141 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, and the first surface of the second pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 157
Dependent Claim
55 words
The semiconductor package of claim 141 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 158
Dependent Claim
35 words
The semiconductor package of claim 141 , wherein the first semiconductor chip assembly is devoid of wire bonds and TAB leads, and the second semiconductor chip assembly is devoid of wire bonds and TAB leads.
Claim 159
Dependent Claim
264 words
The semiconductor package of claim 141 , including: a third semiconductor chip assembly that includes a third semiconductor chip and a third conductive trace, wherein the third chip includes first and second opposing surfaces, the first surface of the third chip includes a third conductive pad, the third conductive trace includes a third routing line and a third pillar, the third routing line is essentially flat and coplanar with the first surface of the third chip and extends within and outside a periphery of the third chip and overlaps and is electrically connected to the third pad, the third pillar includes first and second opposing surfaces and is disposed outside the periphery of the third chip at a distal end of the third routing line and does not extend to the second surface of the third chip, the first surface of the third pillar faces away from the first surface of the third chip, and the second surface of the third pillar is essentially coplanar with the first surface of the third chip; and a second conductive bond disposed outside the peripheries of the second and third chips that contacts and electrically connects the second and third pillars; wherein the first surface of the second chip faces the second surface of the third chip, the first surface of the second pillar faces the second surface of the third pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the third pillar, and the second and third conductive traces have essentially identical shapes and sizes.
Claim 160
Dependent Claim
197 words
A three-dimensional stacked semiconductor package, comprising: a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and has a conical shape and is disposed outside the periphery of the chip, and the first surface of the pillar is essentially parallel to the first surface of the chip; and a plurality of conductive bonds disposed outside the peripheries of the chips that each contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies; wherein for each of the assemblies, the chip is aligned with other chips in the package, and the pillars are aligned with other pillars in the package.
Claim 161
Dependent Claim
197 words
A three-dimensional stacked semiconductor package, comprising: a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and has a conical shape and is disposed outside the periphery of the chip, and the first surface of the pillar is essentially parallel to the first surface of the chip; and a plurality of conductive bonds disposed outside the peripheries of the chips that each contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies; wherein for each of the assemblies, the chip is aligned with other chips in the package, and the pillars are aligned with other pillars in the package.
Claim 162
Dependent Claim
88 words
The semiconductor package of claim 151 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 163
Dependent Claim
27 words
The semiconductor package of claim 151 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 164
Dependent Claim
32 words
The semiconductor package of claim 151 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 165
Dependent Claim
38 words
The semiconductor package of claim 151 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 166
Dependent Claim
58 words
The semiconductor package of claim 151 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 167
Dependent Claim
74 words
The semiconductor package of claim 151 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 168
Dependent Claim
28 words
The semiconductor package of claim 151 , including a single continuous encapsulant that contacts each of the routing lines, each of the pillars and each of the chips.
Claim 169
Dependent Claim
18 words
The semiconductor package of claim 151 , wherein each of the assemblies is essentially identical to one another.
Claim 170
Dependent Claim
18 words
The semiconductor package of claim 151 , wherein the package is devoid of wire bonds and TAB leads.
Claim 171
Independent Claim
393 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then moving the first and second assemblies towards one another while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar, and the bonding material deforms; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 172
Independent Claim
393 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, and the first surface of the first pillar faces away from the first surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, and the first surface of the second pillar faces away from the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then moving the first and second assemblies towards one another while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar, and the bonding material deforms; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 173
Dependent Claim
134 words
The method of claim 161 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and overlaps the first pad, the second routing line is essentially flat and coplanar with the first surface of the second chip and overlaps the second pad, the first pillar is disposed at a distal end of the first routing line, the second pillar is disposed at a distal end of the second routing line, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 174
Dependent Claim
38 words
The method of claim 161 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 175
Dependent Claim
25 words
The method of claim 161 , wherein the first assembly contacts the second surface of the second chip after moving the assemblies towards one another.
Claim 176
Dependent Claim
30 words
The method of claim 161 , wherein the first surface of the first pillar is essentially coplanar with the first surface of the second chip after solidifying the bonding material.
Claim 177
Dependent Claim
41 words
The method of claim 161 , wherein the first pillar does not extend to the second surface of the first chip, and the second pillar does not extend to the second surface of the second chip after solidifying the bonding material.
Claim 178
Dependent Claim
84 words
The method of claim 161 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, and the first surface of the second pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 179
Dependent Claim
19 words
The method of claim 161 , wherein the bonding material is solder paste and the conductive bond is solder.
Claim 180
Dependent Claim
33 words
The method of claim 161 , including forming an encapsulant on the first and second routing lines, the first and second pillars and the first and second chips after solidifying the bonding material.
Claim 181
Dependent Claim
17 words
The method of claim 161 , wherein the package is devoid of wire bonds and TAB leads.
Claim 182
Independent Claim
523 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then applying pressure while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms until the first assembly contacts the second surface of the second chip, at which time the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar and the first and second pillars are separated by the bonding material; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 183
Independent Claim
523 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is essentially coplanar with the first surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then applying pressure while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms until the first assembly contacts the second surface of the second chip, at which time the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar and the first and second pillars are separated by the bonding material; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 184
Dependent Claim
62 words
The method of claim 171 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 185
Dependent Claim
38 words
The method of claim 171 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 186
Dependent Claim
23 words
The method of claim 171 , wherein the first routing line contacts the second surface of the second chip after applying the pressure.
Claim 187
Dependent Claim
36 words
The method of claim 171 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 188
Dependent Claim
84 words
The method of claim 171 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, and the first surface of the second pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 189
Dependent Claim
54 words
The method of claim 171 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 190
Dependent Claim
45 words
The method of claim 171 , wherein the bonding material is solder paste, the conductive bond is solder, and solidifying the bonding material to form the conductive bond includes applying heat to reflow solder particles in the solder paste without applying pressure to the package.
Claim 191
Dependent Claim
33 words
The method of claim 171 , including forming an encapsulant on the first and second routing lines, the first and second pillars and the first and second chips after solidifying the bonding material.
Claim 192
Dependent Claim
17 words
The method of claim 171 , wherein the package is devoid of wire bonds and TAB leads.
Claim 193
Independent Claim
189 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and has a conical shape and is disposed outside the periphery of the chip, and the first surface of the pillar is essentially parallel to the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, and conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies.
Claim 194
Independent Claim
189 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and has a conical shape and is disposed outside the periphery of the chip, and the first surface of the pillar is essentially parallel to the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, and conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies.
Claim 195
Dependent Claim
87 words
The method of claim 181 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 196
Dependent Claim
26 words
The method of claim 181 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 197
Dependent Claim
31 words
The method of claim 181 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 198
Dependent Claim
37 words
The method of claim 181 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 199
Dependent Claim
57 words
The method of claim 181 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 200
Dependent Claim
73 words
The method of claim 181 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 201
Dependent Claim
30 words
The method of claim 181 , including forming an encapsulant that contacts each of the routing lines, each of the pillars and each of the chips after stacking the assemblies.
Claim 202
Dependent Claim
17 words
The method of claim 181 , wherein each of the assemblies is essentially identical to one another.
Claim 203
Dependent Claim
17 words
The method of claim 181 , wherein the package is devoid of wire bonds and TAB leads.
Claim 204
Independent Claim
250 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a single semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and has a conical shape and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar is essentially parallel to and faces away from the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, and the first surface of the pillar faces the second surface of the adjacent lower pillar.
Claim 205
Independent Claim
250 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a single semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and has a conical shape and is disposed outside the periphery of the chip and does not extend to the second surface of the chip, and the first surface of the pillar is essentially parallel to and faces away from the first surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, and the first surface of the pillar faces the second surface of the adjacent lower pillar.
Claim 206
Dependent Claim
87 words
The method of claim 191 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 207
Dependent Claim
26 words
The method of claim 191 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 208
Dependent Claim
31 words
The method of claim 191 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 209
Dependent Claim
37 words
The method of claim 191 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 210
Dependent Claim
57 words
The method of claim 191 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 211
Dependent Claim
73 words
The method of claim 191 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 212
Dependent Claim
30 words
The method of claim 191 , including forming an encapsulant that contacts each of the routing lines, each of the pillars and each of the chips after stacking the assemblies.
Claim 213
Dependent Claim
17 words
The method of claim 191 , wherein each of the assemblies is essentially identical to one another.
Claim 214
Dependent Claim
17 words
The method of claim 191 , wherein the package is devoid of wire bonds and TAB leads.
Claim 215
Dependent Claim
396 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is between the first and second surfaces of the second chip and is closer to the first surface of the second chip than to the second surface of the second chip.
Claim 216
Dependent Claim
396 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; and a conductive bond that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and the first surface of the first pillar is between the first and second surfaces of the second chip and is closer to the first surface of the second chip than to the second surface of the second chip.
Claim 217
Dependent Claim
37 words
The semiconductor package of claim 201 , wherein the first conductive trace consists of the first routing line and the first pillar, and the second conductive trace consists of the second routing line and the second pillar.
Claim 218
Dependent Claim
29 words
The semiconductor package of claim 202 , wherein the first conductive trace is a single continuous metal lead, and the second conductive trace is a single continuous metal lead.
Claim 219
Dependent Claim
25 words
The semiconductor package of claim 203 , wherein the first routing line overlaps the first pad, and the second routing line overlaps the second pad.
Claim 220
Dependent Claim
37 words
The semiconductor package of claim 203 , wherein the first pillar is disposed at a distal end of the first routing line, and the second pillar is disposed at a distal end of the second routing line.
Claim 221
Dependent Claim
20 words
The semiconductor package of claim 201 , wherein the first and second conductive traces have essentially identical shapes and sizes.
Claim 222
Dependent Claim
135 words
The semiconductor package of claim 201 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and overlaps the first pad, the second routing line is essentially flat and coplanar with the first surface of the second chip and overlaps the second pad, the first pillar is disposed at a distal end of the first routing line, the second pillar is disposed at a distal end of the second routing line, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 223
Dependent Claim
24 words
The semiconductor package of claim 201 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip.
Claim 224
Dependent Claim
22 words
The semiconductor package of claim 208 , wherein the second conductive trace includes another pillar within the periphery of the second chip.
Claim 225
Dependent Claim
43 words
The semiconductor package of claim 201 , wherein the first routing line is essentially flat and parallel to the first surface of the first chip, and the second routing line is essentially flat and parallel to the first surface of the second chip.
Claim 226
Dependent Claim
39 words
The semiconductor package of claim 210 , wherein the first routing line is essentially coplanar with the first surface of the first chip, and the second routing line is essentially coplanar with the first surface of the second chip.
Claim 227
Dependent Claim
29 words
The semiconductor package of claim 211 , wherein the first routing line is contiguous with the first pillar, and the second routing line is contiguous with the second pillar.
Claim 228
Dependent Claim
25 words
The semiconductor package of claim 212 , wherein the first routing line overlaps the first pad, and the second routing line overlaps the second pad.
Claim 229
Dependent Claim
20 words
The semiconductor package of claim 201 , wherein the first routing line contacts the second surface of the second chip.
Claim 230
Dependent Claim
24 words
The semiconductor package of claim 201 , wherein the first routing line contacts an adhesive that contacts the second surface of the second chip.
Claim 231
Dependent Claim
45 words
The semiconductor package of claim 201 , wherein the second surface of the first pillar is essentially parallel to the first surface of the first chip, and the second surface of the second pillar is essentially parallel to the first surface of the second chip.
Claim 232
Dependent Claim
45 words
The semiconductor package of claim 216 , wherein the second surface of the first pillar is essentially coplanar with the first surface of the first chip, and the second surface of the second pillar is essentially coplanar with the first surface of the second chip.
Claim 233
Dependent Claim
39 words
The semiconductor package of claim 201 , wherein the first pillar extends orthogonally to the first and second surfaces of the first chip, and the second pillar extends orthogonally to the first and second surfaces of the second chip.
Claim 234
Dependent Claim
47 words
The semiconductor package of claim 201 , wherein the first and second surfaces of the first pillar are separated by a first distance, the first and second surfaces of the second chip are separated by a second distance, and the first and second distances are essentially identical.
Claim 235
Dependent Claim
37 words
The semiconductor package of claim 201 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 236
Dependent Claim
26 words
The semiconductor package of claim 201 , wherein the first surface of the first pillar is essentially parallel to the second surface of the second pillar.
Claim 237
Dependent Claim
26 words
The semiconductor package of claim 201 , wherein the first surface of the first pillar does not extend past the second surface of the second pillar.
Claim 238
Dependent Claim
53 words
The semiconductor package of claim 201 , wherein the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, and the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar.
Claim 239
Dependent Claim
30 words
The semiconductor package of claim 201 , wherein the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the second pillar.
Claim 240
Dependent Claim
23 words
The semiconductor package of claim 201 , wherein the first surface of the first pillar contacts the second surface of the second pillar.
Claim 241
Dependent Claim
49 words
The semiconductor package of claim 201 , wherein the first surface of the first pillar is separated from the second surface of the second pillar, and the conductive bond contacts and is sandwiched between the first surface of the first pillar and the second surface of the second pillar.
Claim 242
Dependent Claim
37 words
The semiconductor package of claim 201 , wherein the first pillar is disposed at a distal end of the first routing line, and the second pillar is disposed at a distal end of the second routing line.
Claim 243
Dependent Claim
49 words
The semiconductor package of claim 201 , wherein the first pillar has a conical shape in which its diameter increases from its first surface to its second surface, and the second pillar has a conical shape in which its diameter increases from its first surface to its second surface.
Claim 244
Dependent Claim
41 words
The semiconductor package of claim 201 , wherein the first pillar has a smaller diameter at its first surface than at its second surface, and the second pillar has a smaller diameter at its first surface than at its second surface.
Claim 245
Dependent Claim
22 words
The semiconductor package of claim 201 , wherein the conductive bond is disposed outside the peripheries of the first and second chips.
Claim 246
Dependent Claim
22 words
The semiconductor package of claim 201 , wherein the conductive bond is the only material that contacts the first and second pillars.
Claim 247
Dependent Claim
27 words
The semiconductor package of claim 201 , wherein the conductive bond is the only material that mechanically attaches the first and second conductive traces to one another.
Claim 248
Dependent Claim
33 words
The semiconductor package of claim 201 , wherein the conductive bond and the first and second conductive traces are the only materials in an electrically conductive path between the first and second pads.
Claim 249
Dependent Claim
32 words
The semiconductor package of claim 201 , wherein the conductive bond is selected from the group consisting of solder, conductive adhesive, conductive paste, electroplated metal, electrolessly plated metal, and a welded joint.
Claim 250
Dependent Claim
55 words
The semiconductor package of claim 201 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 251
Dependent Claim
22 words
The semiconductor package of claim 201 , wherein the first semiconductor chip assembly is essentially identical to the second semiconductor chip assembly.
Claim 252
Dependent Claim
33 words
The semiconductor package of claim 201 , wherein the first surface of the first chip and the second surface of the second chip are separated from one another by at most 30 microns.
Claim 253
Dependent Claim
19 words
The semiconductor package of claim 201 , including a single continuous encapsulant that contacts the first and second chips.
Claim 254
Dependent Claim
246 words
The semiconductor package of claim 201 , including: a third semiconductor chip assembly that includes a third semiconductor chip and a third conductive trace, wherein the third chip includes first and second opposing surfaces, the first surface of the third chip includes a third conductive pad, the third conductive trace includes a third routing line and a third pillar, the third routing line extends within and outside a periphery of the third chip and is electrically connected to the third pad, the third pillar includes first and second opposing surfaces and is disposed outside the periphery of the third chip, the first surface of the third pillar is disposed at a distal end of the third pillar, the first surface of the third pillar faces away from the first surface of the third chip, and the second surface of the third pillar is closer to the first surface of the third chip than to the second surface of the third chip; and a second conductive bond that contacts and electrically connects the second and third pillars; wherein the first surface of the second chip faces the second surface of the third chip, the first surface of the second pillar faces the second surface of the third pillar, and the first surface of the second pillar is between the first and second surfaces of the third chip and is closer to the first surface of the third chip than to the second surface of the third chip.
Claim 255
Dependent Claim
18 words
The semiconductor package of claim 201 , wherein the package is devoid of wire bonds and TAB leads.
Claim 256
Dependent Claim
490 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; and a conductive bond disposed outside the peripheries of the first and second chips that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, the first surface of the first pillar is between the first and second surfaces of the second chip and is closer to the first surface of the second chip than to the second surface of the second chip, and the first and second pillars have essentially identical shapes and sizes.
Claim 257
Dependent Claim
490 words
A three-dimensional stacked semiconductor package, comprising: a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; and a conductive bond disposed outside the peripheries of the first and second chips that contacts and electrically connects the first and second pillars; wherein the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, the first surface of the first pillar is between the first and second surfaces of the second chip and is closer to the first surface of the second chip than to the second surface of the second chip, and the first and second pillars have essentially identical shapes and sizes.
Claim 258
Dependent Claim
51 words
The semiconductor package of claim 241 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, and the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar.
Claim 259
Dependent Claim
39 words
The semiconductor package of claim 241 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 260
Dependent Claim
20 words
The semiconductor package of claim 241 , wherein the first routing line contacts the second surface of the second chip.
Claim 261
Dependent Claim
37 words
The semiconductor package of claim 241 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 262
Dependent Claim
26 words
The semiconductor package of claim 241 , wherein the first surface of the first pillar does not extend past the second surface of the second pillar.
Claim 263
Dependent Claim
107 words
The semiconductor package of claim 241 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar, and the first surface of the first pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 264
Dependent Claim
55 words
The semiconductor package of claim 241 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 265
Dependent Claim
35 words
The semiconductor package of claim 241 , wherein the first semiconductor chip assembly is devoid of wire bonds and TAB leads, and the second semiconductor chip assembly is devoid of wire bonds and TAB leads.
Claim 266
Dependent Claim
305 words
The semiconductor package of claim 241 , including: a third semiconductor chip assembly that includes a third semiconductor chip and a third conductive trace, wherein the third chip includes first and second opposing surfaces, the first surface of the third chip includes a third conductive pad, the third conductive trace includes a third routing line and a third pillar, the third routing line is essentially flat and coplanar with the first surface of the third chip and extends within and outside a periphery of the third chip and overlaps and is electrically connected to the third pad, the third pillar includes first and second opposing surfaces and is disposed outside the periphery of the third chip at a distal end of the third routing line and does not extend to the second surface of the third chip, the first surface of the third pillar is disposed at a distal end of the third pillar, the first surface of the third pillar faces away from the first surface of the third chip, and the second surface of the third pillar is closer to the first surface of the third chip than to the second surface of the third chip; and a second conductive bond disposed outside the peripheries of the second and third chips that contacts and electrically connects the second and third pillars; wherein the first surface of the second chip faces the second surface of the third chip, the first surface of the second pillar faces the second surface of the third pillar, the first surface of the second pillar is between the first and second surfaces of the third chip and is closer to the first surface of the third chip than to the second surface of the third chip, and the second and third conductive traces have essentially identical shapes and sizes.
Claim 267
Dependent Claim
313 words
A three-dimensional stacked semiconductor package, comprising: a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip, the first surface of the pillar is disposed at a distal end of the pillar, the first surface of the pillar faces away from the first surface of the chip, and the second surface of the pillar is closer to the first surface of the chip than to the second surface of the chip; and a plurality of conductive bonds disposed outside the peripheries of the chips that each contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies; wherein for each of the assemblies, the chip is aligned with other chips in the package, and the pillars are aligned with other pillars in the package; and wherein for each of the assemblies above a lowest assembly in the package, the first surfaces of the pillars face the second surfaces of the pillars on the adjacent lower assembly, and the first surfaces of the pillars are between the first and second surfaces of the chip on the adjacent lower assembly and are closer to the first surface of the chip on the adjacent lower assembly than to the second surface of the chip on the adjacent lower assembly.
Claim 268
Dependent Claim
313 words
A three-dimensional stacked semiconductor package, comprising: a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip, the first surface of the pillar is disposed at a distal end of the pillar, the first surface of the pillar faces away from the first surface of the chip, and the second surface of the pillar is closer to the first surface of the chip than to the second surface of the chip; and a plurality of conductive bonds disposed outside the peripheries of the chips that each contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies; wherein for each of the assemblies, the chip is aligned with other chips in the package, and the pillars are aligned with other pillars in the package; and wherein for each of the assemblies above a lowest assembly in the package, the first surfaces of the pillars face the second surfaces of the pillars on the adjacent lower assembly, and the first surfaces of the pillars are between the first and second surfaces of the chip on the adjacent lower assembly and are closer to the first surface of the chip on the adjacent lower assembly than to the second surface of the chip on the adjacent lower assembly.
Claim 269
Dependent Claim
88 words
The semiconductor package of claim 251 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 270
Dependent Claim
27 words
The semiconductor package of claim 251 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 271
Dependent Claim
32 words
The semiconductor package of claim 251 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 272
Dependent Claim
38 words
The semiconductor package of claim 251 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 273
Dependent Claim
58 words
The semiconductor package of claim 251 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 274
Dependent Claim
74 words
The semiconductor package of claim 251 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 275
Dependent Claim
28 words
The semiconductor package of claim 251 , including a single continuous encapsulant that contacts each of the routing lines, each of the pillars and each of the chips.
Claim 276
Dependent Claim
18 words
The semiconductor package of claim 251 , wherein each of the assemblies is essentially identical to one another.
Claim 277
Dependent Claim
18 words
The semiconductor package of claim 251 , wherein the package is devoid of wire bonds and TAB leads.
Claim 278
Independent Claim
496 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then moving the first and second assemblies towards one another while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars, wherein the first surface of the first pillar is between the first and second surfaces of the second chip and is closer to the first surface of the second chip than to the second surface of the second chip.
Claim 279
Independent Claim
496 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line extends within and outside a periphery of the first chip and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line extends within and outside a periphery of the second chip and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then moving the first and second assemblies towards one another while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars, wherein the first surface of the first pillar is between the first and second surfaces of the second chip and is closer to the first surface of the second chip than to the second surface of the second chip.
Claim 280
Dependent Claim
134 words
The method of claim 261 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and overlaps the first pad, the second routing line is essentially flat and coplanar with the first surface of the second chip and overlaps the second pad, the first pillar is disposed at a distal end of the first routing line, the second pillar is disposed at a distal end of the second routing line, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 281
Dependent Claim
38 words
The method of claim 261 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 282
Dependent Claim
25 words
The method of claim 261 , wherein the first assembly contacts the second surface of the second chip after moving the assemblies towards one another.
Claim 283
Dependent Claim
39 words
The method of claim 261 , wherein the first surface of the first pillar is much closer to the first surface of the second chip than to the second surface of the second chip after solidifying the bonding material.
Claim 284
Dependent Claim
41 words
The method of claim 261 , wherein the first pillar does not extend to the second surface of the first chip, and the second pillar does not extend to the second surface of the second chip after solidifying the bonding material.
Claim 285
Dependent Claim
113 words
The method of claim 261 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar, and after positioning the first and second assemblies, the first surface of the first pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 286
Dependent Claim
19 words
The method of claim 261 , wherein the bonding material is solder paste and the conductive bond is solder.
Claim 287
Dependent Claim
33 words
The method of claim 261 , including forming an encapsulant on the first and second routing lines, the first and second pillars and the first and second chips after solidifying the bonding material.
Claim 288
Dependent Claim
17 words
The method of claim 261 , wherein the package is devoid of wire bonds and TAB leads.
Claim 289
Independent Claim
589 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then applying pressure while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms until the first assembly contacts the second surface of the second chip, at which time the first surface of the first pillar is between the first and second surfaces of the second chip, closer to the first surface of the second chip than to the second surface of the second chip and separated from the second surface of the second pillar by the bonding material; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 290
Independent Claim
589 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a first semiconductor chip assembly that includes a first semiconductor chip and a first conductive trace, wherein the first chip includes first and second opposing surfaces, the first surface of the first chip includes a first conductive pad, the first conductive trace includes a first routing line and a first pillar, the first routing line is essentially flat and coplanar with the first surface of the first chip and extends within and outside a periphery of the first chip and overlaps and is electrically connected to the first pad, the first pillar includes first and second opposing surfaces and is disposed outside the periphery of the first chip at a distal end of the first routing line and does not extend to the second surface of the first chip, the first surface of the first pillar is disposed at a distal end of the first pillar, the first surface of the first pillar faces away from the first surface of the first chip, and the second surface of the first pillar is closer to the first surface of the first chip than to the second surface of the first chip; providing a second semiconductor chip assembly that includes a second semiconductor chip and a second conductive trace, wherein the second chip includes first and second opposing surfaces, the first surface of the second chip includes a second conductive pad, the second conductive trace includes a second routing line and a second pillar, the second routing line is essentially flat and coplanar with the first surface of the second chip and extends within and outside a periphery of the second chip and overlaps and is electrically connected to the second pad, the second pillar includes first and second opposing surfaces and is disposed outside the periphery of the second chip at a distal end of the second routing line and does not extend to the second surface of the second chip, the first surface of the second pillar is disposed at a distal end of the second pillar, the first surface of the second pillar faces away from the first surface of the second chip, and the second surface of the second pillar is closer to the first surface of the second chip than to the second surface of the second chip; then positioning the first and second assemblies such that the first surface of the first chip faces the second surface of the second chip, the first surface of the first pillar faces the second surface of the second pillar, and a bonding material is disposed between and contacts the first surface of the first pillar and the second surface of the second pillar; then applying pressure while the bonding material is non-solidified such that the first surface of the first chip moves towards the second surface of the second chip, the first surface of the first pillar moves towards the second surface of the second pillar and the bonding material deforms until the first assembly contacts the second surface of the second chip, at which time the first surface of the first pillar is between the first and second surfaces of the second chip, closer to the first surface of the second chip than to the second surface of the second chip and separated from the second surface of the second pillar by the bonding material; and then solidifying the bonding material to provide a conductive bond that contacts and electrically connects the first and second pillars.
Claim 291
Dependent Claim
62 words
The method of claim 271 , wherein the first conductive trace is a single continuous metal lead that consists of the first routing line and the first pillar, the second conductive trace is a single continuous metal lead that consists of the second routing line and the second pillar, and the first and second conductive traces have essentially identical shapes and sizes.
Claim 292
Dependent Claim
38 words
The method of claim 271 , wherein the first conductive trace is devoid of a pillar within the periphery of the first chip, and the second conductive trace includes another pillar within the periphery of the second chip.
Claim 293
Dependent Claim
23 words
The method of claim 271 , wherein the first routing line contacts the second surface of the second chip after applying the pressure.
Claim 294
Dependent Claim
36 words
The method of claim 271 , wherein the first pillar does not extend to the first surface of the first chip, and the second pillar does not extend to the first surface of the second chip.
Claim 295
Dependent Claim
110 words
The method of claim 271 , wherein the first pillar has a diameter that increases from its first surface to its second surface, the second pillar has a diameter that increases from its first surface to its second surface, the first surface of the first pillar is concentrically disposed within a surface area of the second surface of the first pillar, the first surface of the second pillar is concentrically disposed within a surface area of the second surface of the second pillar, and after positioning the assemblies, the first surface of the first pillar is concentrically disposed within the surface area of the second surface of the second pillar.
Claim 296
Dependent Claim
54 words
The method of claim 271 , wherein the first semiconductor chip assembly includes a first insulative adhesive between and in contact with the first pad and the first routing line, and the second semiconductor chip assembly includes a second insulative adhesive between and in contact with the second pad and the second routing line.
Claim 297
Dependent Claim
45 words
The method of claim 271 , wherein the bonding material is solder paste, the conductive bond is solder, and solidifying the bonding material to form the conductive bond includes applying heat to reflow solder particles in the solder paste without applying pressure to the package.
Claim 298
Dependent Claim
33 words
The method of claim 271 , including forming an encapsulant on the first and second routing lines, the first and second pillars and the first and second chips after solidifying the bonding material.
Claim 299
Dependent Claim
17 words
The method of claim 271 , wherein the package is devoid of wire bonds and TAB leads.
Claim 300
Independent Claim
306 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip, the first surface of the pillar is disposed at a distal end of the pillar, the first surface of the pillar faces away from the first surface of the chip, and the second surface of the pillar is closer to the first surface of the chip than to the second surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip and is closer to the first surface of the adjacent lower chip than to the second surface of the adjacent lower chip.
Claim 301
Independent Claim
306 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip, the first surface of the pillar is disposed at a distal end of the pillar, the first surface of the pillar faces away from the first surface of the chip, and the second surface of the pillar is closer to the first surface of the chip than to the second surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip and is closer to the first surface of the adjacent lower chip than to the second surface of the adjacent lower chip.
Claim 302
Dependent Claim
87 words
The method of claim 281 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 303
Dependent Claim
26 words
The method of claim 281 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 304
Dependent Claim
31 words
The method of claim 281 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 305
Dependent Claim
37 words
The method of claim 281 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 306
Dependent Claim
57 words
The method of claim 281 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 307
Dependent Claim
73 words
The method of claim 281 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 308
Dependent Claim
30 words
The method of claim 281 , including forming an encapsulant that contacts each of the routing lines, each of the pillars and each of the chips after stacking the assemblies.
Claim 309
Dependent Claim
17 words
The method of claim 281 , wherein each of the assemblies is essentially identical to one another.
Claim 310
Dependent Claim
17 words
The method of claim 281 , wherein the package is devoid of wire bonds and TAB leads.
Claim 311
Independent Claim
323 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a single semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip, the first surface of the pillar is disposed at a distal end of the pillar, the first surface of the pillar is essentially parallel to and faces away from the first surface of the chip, and the second surface of the pillar is essentially parallel to the first surface of the chip and is closer to the first surface of the chip than to the second surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip and is closer to the first surface of the adjacent lower chip than to the second surface of the adjacent lower chip.
Claim 312
Independent Claim
323 words
A method of making a three-dimensional stacked semiconductor package, comprising: providing a plurality of semiconductor chip assemblies, wherein each of the assemblies includes a single semiconductor chip and a plurality of conductive traces, wherein the chip includes first and second opposing surfaces, the first surface of the chip includes a plurality of conductive pads, each of the conductive traces includes a routing line and a pillar, the routing line is essentially flat and extends within a periphery of the chip and overlaps and is electrically connected to a corresponding one of the pads, the routing line extends outside the periphery of the chip and is contiguous with the pillar, the pillar includes first and second opposing surfaces and is disposed outside the periphery of the chip, the first surface of the pillar is disposed at a distal end of the pillar, the first surface of the pillar is essentially parallel to and faces away from the first surface of the chip, and the second surface of the pillar is essentially parallel to the first surface of the chip and is closer to the first surface of the chip than to the second surface of the chip; and stacking the assemblies such that the chips are aligned with one another, the pillars are aligned with one another, conductive bonds outside the peripheries of the chips contact and electrically connect corresponding pairs of the pillars on separate ones of the assemblies, and for each of the assemblies above a lowest assembly in the package, the first surface of the chip faces the second surface of the adjacent lower chip, the first surface of the pillar faces the second surface of the adjacent lower pillar, and the first surface of the pillar is between the first and second surfaces of the adjacent lower chip and is closer to the first surface of the adjacent lower chip than to the second surface of the adjacent lower chip.
Claim 313
Dependent Claim
87 words
The method of claim 291 , wherein for each of the assemblies, each of the conductive traces is a single continuous metal lead that consists of the routing line and the pillar, the routing line is essentially flat and coplanar with the first surface of the chip, the pillar is disposed at a distal end of the routing line, and the second surface of the pillar is essentially coplanar with the first surface of the chip and does not extend to the second surface of the chip.
Claim 314
Dependent Claim
26 words
The method of claim 291 , wherein for each of the assemblies, an insulative adhesive is sandwiched between and contacts each pad and each routing line.
Claim 315
Dependent Claim
31 words
The method of claim 291 , wherein for each of the assemblies above the lowest assembly in the package, each routing line contacts the second surface of the adjacent lower chip.
Claim 316
Dependent Claim
37 words
The method of claim 291 , wherein for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is essentially parallel to the second surface of the adjacent lower pillar.
Claim 317
Dependent Claim
57 words
The method of claim 291 , wherein for each of the assemblies above the lowest assembly in the package, each of the conductive traces is devoid of a pillar within the periphery of the chip, and for the lowest assembly in the package, each of the conductive traces includes another pillar within the periphery of the chip.
Claim 318
Dependent Claim
73 words
The method of claim 291 , wherein each pillar has a diameter that increases from its first surface to its second surface such that its first surface is concentrically disposed within a surface area of its second surface, and for each of the assemblies above the lowest assembly in the package, the first surface of each pillar is concentrically disposed within a surface area of the second surface of the adjacent lower pillar.
Claim 319
Dependent Claim
30 words
The method of claim 291 , including forming an encapsulant that contacts each of the routing lines, each of the pillars and each of the chips after stacking the assemblies.
Claim 320
Dependent Claim
17 words
The method of claim 291 , wherein each of the assemblies is essentially identical to one another.
Claim 321
Dependent Claim
17 words
The method of claim 291 , wherein the package is devoid of wire bonds and TAB leads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-01-20 | 2006-07-22 | 2007-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-20 | 2010-07-22 | 2011-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-20 | 2014-07-22 | 2015-01-21 | $7700.00 | Window Closed / Lapsed |