Stacked chip package device employing a plurality of lead on chip type semiconductor chips

Claim 1

A stacked chip package comprising: an upper part comprising an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip, the active surface of the upper semiconductor chip facing an upper lead frame and facing away from a lower lead frame; said upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part comprising a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip, the active surface of the lower semiconductor chip facing both said lower lead frame and upper lead frames; said lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device, wherein the leads of the upper lead frame are formed to directly contact top surfaces of the inner leads of the lower lead frame, so that the upper and the lower parts can be electrically interconnected; and an insulating adhesive film interposed between and simultaneously contacting the bottom surface of the upper semiconductor chip along entire lengths of two parallel edges of the chip, and the top surfaces of the inner leads of the lower lead frame.