Abstract A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.
A gate electrode comprising: a gate layer disposed above a substrate; a conductive layer disposed on said gate layer, said conductive layer extending beyond edges of said gate layer; thin first spacers having lower portions disposed adjacent to opposite sides of said gate layer and upper portions disposed adjacent to opposite sides of said conductive layer, said upper portions curved away from said lower portions; and thick second spacers disposed adjacent to said lower portions of said thin first spacers, said thick second spacers each comprising a partial recess to create a thin second spacer wall adjacent to said upper portion of said thin first spacers.
Claim 2
Dependent Claim
106 words
A gate electrode comprising: a gate layer disposed above a substrate; a conductive layer disposed on said gate layer, said conductive layer extending beyond edges of said gate layer; thin first spacers having lower portions disposed adjacent to opposite sides of said gate layer and upper portions disposed adjacent to opposite sides of said conductive layer, said upper portions curved away from said lower portions; and thick second spacers disposed adjacent to said lower portions of said thin first spacers, said thick second spacers each comprising a partial recess to create a thin second spacer wall adjacent to said upper portion of said thin first spacers.
Claim 3
Dependent Claim
12 words
The gate electrode of claim 1 wherein said gate layer comprises polysilicon.
Claim 4
Dependent Claim
12 words
The gate electrode of claim 2 wherein said conductive layer comprises polycide.
Claim 5
Dependent Claim
13 words
The gate electrode of claim 3 wherein said thin first spacers comprise oxide.
Claim 6
Dependent Claim
13 words
The gate electrode of claim 4 wherein said thick second spacers comprise nitride.
Claim 7
Dependent Claim
15 words
The gate electrode of claim 5 wherein said polycide comprises titanium salicide (TiSi 2 ).
Claim 8
Dependent Claim
68 words
A gate electrode comprising: a gate layer disposed above a substrate; a conductive layer disposed over said gate layer; and a spacer structure having lower portions disposed adjacent to opposite sides of said gate layer and upper portions disposed adjacent to opposite sides of said conductive layer, said conductive layer extending beyond edges of said gate layer said upper portions being flexible and curved away from lower portions.
Claim 9
Dependent Claim
68 words
A gate electrode comprising: a gate layer disposed above a substrate; a conductive layer disposed over said gate layer; and a spacer structure having lower portions disposed adjacent to opposite sides of said gate layer and upper portions disposed adjacent to opposite sides of said conductive layer, said conductive layer extending beyond edges of said gate layer said upper portions being flexible and curved away from lower portions.
Claim 10
Dependent Claim
38 words
The gate electrode of claim 7 wherein said lower portion comprises a thin first spacer layer and a thick second spacer layer and said upper portion comprises said thin first spacer layer and a thin second spacer wall.