US5696012A
Expired / Lapsed
US
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Fabrication method of semiconductor memory device containing CMOS transistors
Assignee: Mosaid Technologies Inc
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Filing: 1996-12-24
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Granted: 1997-12-09
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Expires: 2016-12-24
Abstract
Abstract A fabrication method for a semiconductor memory device which remarkably improves a short-channel characteristic, and increases a driving electric current of the device by differently forming the thickness of side wall spacers formed at the sides of polysilicon gates in nMOS and pMOS regions, includes forming a gate insulating film on a semiconductor substrate having first and second regions, forming first and second gate electrodes in the first and second regions, respectively, on the substrate, forming a first conductive low concentration impurity area at the sides of the first gate electrode, forming a second conductive low concentration impurity area at the sides of the second gate electrode, forming a first insulating film on the substrate and a second insulating film on the first insulating film, stripping the second insulating film in the first region, forming first sidewall spacers at the sides of the first gate electrode, forming a first conductive high concentration impurity area in the substrate at the sides of the first gate electrode, forming second sidewall spacers composed of the first and second insulating films at the sides of the second gate electrode in the second region, and forming a second conductive high concentration impurity area in the substrate at the sides of the second gate electrode.
Inventors
- 👤 Jeong-Hwan Son
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:23
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
239 words
A fabrication method for a semiconductor memory device, comprising: forming a gate insulating film on a semiconductor substrate having first and second regions; forming first and second gate electrodes in the first and second regions, respectively, on the substrate; forming a first conductive low concentration impurity area in the substrate of the first region at the sides of the first gate electrode; forming a second conductive low concentration impurity region in the second region on the substrate at the sides of the second gate electrode; forming a first insulating film on the substrate having the first and second gate electrodes thereon and a second insulating film on the first insulating film; stripping the second insulating film in the first region; forming first sidewall spacers at the sides of the first gate electrode by performing an anisotropic etching on the first insulating film in the first region; forming a first conductive high concentration impurity area in the first region of the subtrate at the sides of the first gate electrode having the first sidewall spacers; forming second sidewall spacers composed of the first and second insulating films at the sides of the second gate electrode by performing an anisotropic etching on the first and second insulating films in the second region; and forming a second conductive high concentration impurity region in the substrate of the second region at the sides of the second gate electrode having the second sidewall spacers.
Claim 2
Dependent Claim
239 words
A fabrication method for a semiconductor memory device, comprising: forming a gate insulating film on a semiconductor substrate having first and second regions; forming first and second gate electrodes in the first and second regions, respectively, on the substrate; forming a first conductive low concentration impurity area in the substrate of the first region at the sides of the first gate electrode; forming a second conductive low concentration impurity region in the second region on the substrate at the sides of the second gate electrode; forming a first insulating film on the substrate having the first and second gate electrodes thereon and a second insulating film on the first insulating film; stripping the second insulating film in the first region; forming first sidewall spacers at the sides of the first gate electrode by performing an anisotropic etching on the first insulating film in the first region; forming a first conductive high concentration impurity area in the first region of the subtrate at the sides of the first gate electrode having the first sidewall spacers; forming second sidewall spacers composed of the first and second insulating films at the sides of the second gate electrode by performing an anisotropic etching on the first and second insulating films in the second region; and forming a second conductive high concentration impurity region in the substrate of the second region at the sides of the second gate electrode having the second sidewall spacers.
Claim 3
Dependent Claim
28 words
The fabrication method of claim 1, wherein the first insulating film is composed of an oxide film, and the second insulating film is composed of a nitride film.
Claim 4
Dependent Claim
28 words
The fabrication method of claim 1, wherein the first insulating film is composed of a nitride film, and the second insulating film is composed of an oxide film.
Claim 5
Dependent Claim
24 words
The fabrication method of claim 1, wherein the first conductive impurity is an n-type impurity, and the second conductive impurity is a p-type impurity.
Claim 6
Dependent Claim
66 words
The fabrication method of claim 1, wherein the steps for forming the first sidewall spacers comprise: forming the first insulating film; forming a photoresist film on the second insulating film after forming the second insulating film on the first insulating film; stripping the photoresist film in the first region; and performing an anisotropic etching on the second insulating film, using the photoresist film as a mask.
Claim 7
Dependent Claim
117 words
The fabrication method of claim 1, wherein the steps for forming the second side wall spacers comprise: forming a photoresist film on the second insulating film in the first and second regions; forming sidewall spacers composed of the second insulating film on the first insulating film at the sides of the second gate electrode by performing an anisotropic etching on the second insulating film, using the photoresist film as a mask; and forming sidewall spacers composed of the first insulating film between the sides of the second gate electrode and the sidewall spacers composed of the second insulating film by etching the first insulating film, using as a mask the photoresist film and the second insulating film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |