US5518945A
Expired / Lapsed
US
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Method of making a diffused lightly doped drain device with built in etch stop
Assignee: International Business Machines Corp
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Filing: 1995-05-05
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Granted: 1996-05-21
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Expires: 2015-05-05
Abstract
Abstract A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer of nitride is then deposited on the conformal doped layer. The nitride layer is etched, with the etch stopping on the conformal doped layer, thereby forming nitride spacers. Deep source and drain regions are formed by either ion implantation or diffusion. The device is then heat treated so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region. The method is applicable to N-substrate (P-channel), P-substrate (N-channel), and complementary metal oxide semiconductor (CMOS) devices.
Inventors
- 👤 John A. Bracchitta
- 👤 Gabriel Hartstein
- 👤 Stephen A. Mongeon
- 👤 Anthony C. Speranza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/144; Y10S438/00; Y10S438/975
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A method of fabricating a lightly doped drain MOSFET device, the method comprising the steps of: forming a gate electrode on a substrate; depositing a first conformal doped layer on the gate electrode; depositing a conformal layer of nitride on the first conformal doped layer; etching the nitride layer to form nitride spacers, said etching stopping on the first conformal doped layer; removing said first conformal doped layer everywhere except under said nitride spacers; forming deep source and drain regions; and heat treating the device so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region.
Claim 2
Independent Claim
102 words
A method of fabricating a lightly doped drain MOSFET device, the method comprising the steps of: forming a gate electrode on a substrate; depositing a first conformal doped layer on the gate electrode; depositing a conformal layer of nitride on the first conformal doped layer; etching the nitride layer to form nitride spacers, said etching stopping on the first conformal doped layer; removing said first conformal doped layer everywhere except under said nitride spacers; forming deep source and drain regions; and heat treating the device so that light diffusion occurs under the nitride spacers and heavy diffusion occurs outside the spacer region.
Claim 3
Dependent Claim
25 words
A method as recited in claim 1, wherein the first conformal doped layer is Boron Silicate Glass (BSG) and the device is a P-channel MOSFET.
Claim 4
Dependent Claim
35 words
A method as recited in claim 1, wherein the first conformal doped layer is selected from the group consisting of Phosphorous Silicate Glass (PSG) and arsenic doped glass, and the device is an N-channel MOSFET.
Claim 5
Dependent Claim
19 words
A method as recited in claim 1, wherein the deep source and drain regions are formed by ion implantation.
Claim 6
Dependent Claim
24 words
A method as recited in claim 1, further including the step of depositing a second conformal doped layer after the nitride spacers are formed.
Claim 7
Dependent Claim
18 words
A method as recited in claim 5, wherein the deep source and drain regions are formed by diffusion.
Claim 8
Dependent Claim
20 words
A method recited in claim 1, wherein the heat treating step is performed at a temperature of about 900°-1000° C.
Claim 9
Dependent Claim
18 words
A method as recited in claim 1, wherein the device is a complementary metal oxide semiconductor (CMOS) device.
Claim 10
Dependent Claim
29 words
A method recited in claim 1, further including the step of oxidizing surfaces of the gate electrode prior to depositing the first conformal doped layer on the gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |