US6468906B1
Expired / Lapsed
US
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Passivation of copper interconnect surfaces with a passivating metal layer
Assignee: National University of Singapore
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Filing: 2000-07-14
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Granted: 2002-10-22
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Expires: 2020-07-14
Abstract
Abstract An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.
Inventors
- 👤 Lap Chan
- 👤 Kuan Pei Yap
- 👤 Kheng Chok Tee
- 👤 Flora S. Ip
- 👤 Wye Boon Loh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:57
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/037; H10W20/047; H10W20/049; H10W20/055; H10W20/064
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
90 words
An interconnect line on a dielectric layer on a semiconductor device comprising: an interconnect trench hole formed in said dielectric layer, said interconnect trench hole having walls, and a bottom formed in said dielectric layer, a diffusion barrier formed on said walls and formed on said bottom of said interconnect trench hole, said interconnect trench hole filled with a copper metal line, and a copper metal alloy layer formed on the surface of said copper metal line encapsulating said copper metal line at the top of said interconnect trench hole.
Claim 2
Dependent Claim
90 words
An interconnect line on a dielectric layer on a semiconductor device comprising: an interconnect trench hole formed in said dielectric layer, said interconnect trench hole having walls, and a bottom formed in said dielectric layer, a diffusion barrier formed on said walls and formed on said bottom of said interconnect trench hole, said interconnect trench hole filled with a copper metal line, and a copper metal alloy layer formed on the surface of said copper metal line encapsulating said copper metal line at the top of said interconnect trench hole.
Claim 3
Dependent Claim
32 words
A device in accordance with claim 1 wherein: said device has a top surface planarized to have a coplanarity of said copper metal alloy layer with the topography of said dielectric layer.
Claim 4
Dependent Claim
107 words
A device in accordance with claim 1 comprising an interconnect line on a substrate surface wherein: an upper dielectric layer is formed on said device above on said dielectric layer and on said copper metal alloy layer, an upper interconnect trench hole formed in said upper IMD layer, said upper interconnect trench hole having walls, a top and a bottom extending to the surface of said passivating metal layer, an upper diffusion barrier formed on said walls and formed on said passivating metal layer at said bottom of said upper interconnect trench hole, and said upper interconnect trench hole being filled with an upper copper metal line.
Claim 5
Dependent Claim
83 words
An interconnect line on an IMD layer on a semiconductor device comprising: an interconnect trench hole in said IMD layer, said interconnect trench hole having walls and a bottom in said IMD layer, a diffusion barrier on said walls and said bottom of said trench hole, said interconnect trench hole being filled with copper metal line layer, and a passivating copper metal alloy on the surface of said copper metal line encapsulating said copper metal line at the top of said trench hole.
Claim 6
Dependent Claim
83 words
An interconnect line on an IMD layer on a semiconductor device comprising: an interconnect trench hole in said IMD layer, said interconnect trench hole having walls and a bottom in said IMD layer, a diffusion barrier on said walls and said bottom of said trench hole, said interconnect trench hole being filled with copper metal line layer, and a passivating copper metal alloy on the surface of said copper metal line encapsulating said copper metal line at the top of said trench hole.
Claim 7
Dependent Claim
22 words
A device in accordance with claim 4 wherein: said alloy and said IMD layer have been planarized to have a coplanar surfaces.
Claim 8
Dependent Claim
45 words
A device in accordance with claim 4 wherein: said passivating copper metal alloy on the surface of said copper metal line encapsulating said copper metal line at the top of said interconnect trench hole has a thickness from about 50 Å to about 300 Å.
Claim 9
Dependent Claim
79 words
A device in accordance with claim 4 comprising an interconnect line on a substrate surface wherein: said IMD layer has a top surface, said diffusion barrier layer covering said top surface of said IMD layer, the surface of said device having been polished to planarize said diffusion barrier layer and said copper metal line to achieve coplanarity of said top surface of said device, and an alloy of said copper and said passivating metal formed at the interface thereof.
Claim 10
Dependent Claim
96 words
A device in accordance with claim 4 comprising an interconnect line on a substrate surface wherein: an upper IMD layer is formed on said device above said passivating metal layer, an upper interconnect trench hole in said upper IMD layer, said upper interconnect trench hole having walls, a top and a bottom extending to the surface of said passivating metal layer, an upper diffusion barrier on said walls and said passivating metal layer at said bottom of said upper interconnect trench hole, and said upper interconnect trench hole being filled with an upper copper metal line.
Claim 11
Dependent Claim
125 words
An interconnect line on an IMD layer on a semiconductor device comprising: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, and said alloy layer having been planarized to be coplanar with said IMD layer.
Claim 12
Dependent Claim
125 words
An interconnect line on an IMD layer on a semiconductor device comprising: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, and said alloy layer having been planarized to be coplanar with said IMD layer.
Claim 13
Dependent Claim
148 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, said alloy layer planarized to be coplanar with said IMD layer, and said passivating metal layer comprises a metal selected from the group consisting of aluminum, platinum and palladium.
Claim 14
Dependent Claim
148 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, said alloy layer planarized to be coplanar with said IMD layer, and said passivating metal layer comprises a metal selected from the group consisting of aluminum, platinum and palladium.
Claim 15
Dependent Claim
158 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, said alloy layer planarized to be coplanar with said IMD layer, said copper is deposited by a process selected from CVD, IMP, electroless and electroplating, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium.
Claim 16
Dependent Claim
158 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, said alloy layer planarized to be coplanar with said IMD layer, said copper is deposited by a process selected from CVD, IMP, electroless and electroplating, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium.
Claim 17
Dependent Claim
156 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, said alloy layer planarized to be coplanar with said IMD layer, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium deposited to a thickness from about 50 Å to about 300 Å.
Claim 18
Dependent Claim
156 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, a top and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole and on said top surface of said IMD layer, a deposit of a copper metal line layer covering said diffusion layer and filling said interconnect trench hole with said copper metal line, said copper metal line having a surface covered by an alloy layer of a passivating metal alloy of copper with a passivating metal, said alloy layer planarized to be coplanar with said IMD layer, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium deposited to a thickness from about 50 Å to about 300 Å.
Claim 19
Dependent Claim
169 words
A device in accordance with claim 9 comprising an interconnect line on a substrate surface wherein: said copper was deposited by a process selected from the group consisting of CVD, IMP, electroless and electroplating, said passivating metal layer comprises a metal selected from the group consisting of aluminum, platinum and palladium deposited to a thickness from about 50 Å to about 300 Å, an upper IMD layer is formed of a spin on polymer material on said device above said passivating metal layer, an upper interconnect trench hole in said upper IMD layer, said upper interconnect trench hole having walls, a top and a bottom extending to the surface of said passivating metal layer, an upper diffusion barrier on said walls and said passivating metal layer at said bottom of said upper interconnect trench hole said upper diffusion barrier comprising a refractory metal nitride selected from the group consisting of TiN, TaN and WN, and said upper interconnect trench hole has been filled with an upper copper metal line.
Claim 20
Dependent Claim
121 words
An interconnect line on an IMD layer on a semiconductor device comprising: said IMD layer having a top surface, an interconnect trench hole formed in said IMD layer, said interconnect trench hole having walls, and a bottom formed in said IMD layer, a diffusion barrier formed on said walls, and formed on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal having been planarized with said IMD layer, and a passivating metal layer formed on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration.
Claim 21
Dependent Claim
121 words
An interconnect line on an IMD layer on a semiconductor device comprising: said IMD layer having a top surface, an interconnect trench hole formed in said IMD layer, said interconnect trench hole having walls, and a bottom formed in said IMD layer, a diffusion barrier formed on said walls, and formed on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal having been planarized with said IMD layer, and a passivating metal layer formed on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration.
Claim 22
Dependent Claim
134 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal planarized with said IMD layer, a passivating metal layer on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium.
Claim 23
Dependent Claim
134 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal planarized with said IMD layer, a passivating metal layer on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium.
Claim 24
Dependent Claim
148 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal planarized with said IMD layer, a passivating metal layer on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration, said copper is deposited by a process selected from CVD, IMP, electroless and electroplating, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium.
Claim 25
Dependent Claim
148 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal planarized with said IMD layer, a passivating metal layer on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration, said copper is deposited by a process selected from CVD, IMP, electroless and electroplating, and said passivating metal layer comprises a metal selected from aluminum, platinum and palladium.
Claim 26
Dependent Claim
150 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal planarized with said IMD layer, a passivating metal layer on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration, and said passivating metal layer comprises a metal selected from the group consisting of aluminum, platinum and palladium deposited to a thickness from about 200 Å to about 300 Å.
Claim 27
Dependent Claim
150 words
An interconnect line on an IMD layer on a semiconductor device comprising an interconnect line on a substrate surface wherein: said IMD layer having a top surface, an interconnect trench hole in said IMD layer, said interconnect trench hole having walls, and a bottom in said IMD layer, a diffusion barrier on said walls, on said bottom of said interconnect trench hole, a deposit of a copper metal layer covering said diffusion layer and filling said interconnect trench hole with a copper metal deposit, said copper metal planarized with said IMD layer, a passivating metal layer on the surface of said copper metal deposit encapsulating said copper metal at the top of said interconnect trench hole in a self-aligned configuration, and said passivating metal layer comprises a metal selected from the group consisting of aluminum, platinum and palladium deposited to a thickness from about 200 Å to about 300 Å.
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