US5950102A
Expired / Lapsed
US
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Method for fabricating air-insulated multilevel metal interconnections for integrated circuits
Assignee: Industrial Technology Research Institute
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Filing: 1997-02-03
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Granted: 1999-09-07
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Expires: 2017-02-03
Abstract
Abstract A method for making air-insulated planar metal interconnections having low interlevel capacitance with improved RC time delays for integrated circuits is achieved. The method involves using a multilayer of negative and positive photoresists in which open regions are developed in the negative photoresist for the metal interconnections, and open regions are developed in the positive photoresist for via holes. The open regions are then filled with a Ti/TiN diffusion barrier deposited at room temperature and an electroless plated copper, and polished back using a Dual Damazene to form the interconnecting metal level and the via hole stud. The method is repeated several times to form multilevel metal interconnections. The remaining photoresist is then totally removed by oxygen ashing to leave a free-standing multilevel metal interconnection structure that is conformally coated with a thin Al 2 O 3 passivation layer and having air insulation. This results in a much lower inter- and intralevel capacitance and improved circuit performance.
Inventors
- 👤 William W. Y. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/072; H10W20/40; H10W20/45; H10W20/46
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
391 words
A method for fabricating air-insulated metal interconnections on a substrate comprising the steps of: providing a substrate having device areas surrounded and electrically insulated from each other by field oxide regions, said device areas having partially completed devices formed from a patterned first polysilicon layer; depositing a first insulating layer on said partially completed devices on said substrate; planarizing said first insulating layer; depositing a second insulating layer on said first insulating layer; forming contact holes in said first and second insulating layers to said patterned first polysilicon layer and to said device areas on said substrate; filling selectively said contact holes with a first conducting layer and thereby forming metal plugs; depositing a first negative photoresist layer on said second insulating layer and on said metal plugs; patterning said first negative photoresist layer and forming open regions extending over said metal plugs; depositing a conformal second conducting layer on said first negative photoresist layer and in said open regions electrically contacting said metal plugs; depositing a third conducting layer over said second conducting layer sufficiently thick to fill said open regions in said first negative photoresist layer; planarizing said third conducting layer leaving portions of said third conducting layer in said openings while removing said third conducting layer over and to said first negative photoresist layer thereby forming planar first metal interconnections; depositing a positive photoresist layer over said metal interconnections; depositing a second negative photoresist layer on said positive photoresist layer; patterning said second negative photoresist layer leaving open regions over areas of said positive photoresist where second metal interconnections are desired; exposing and developing in said positive photoresist layer and forming via holes to said first metal interconnections; depositing a conformal fourth conducting layer on said second negative photoresist layer and in said open regions in said second negative photoresist layer; depositing a fifth conducting layer over said fourth conducting layer sufficiently thick to fill said open regions in said second negative photoresist layer; planarizing said fifth conducting layer leaving portions of said fifth conducting layer in said openings while removing said fourth conducting layer over and to said second negative photoresist layer thereby forming said desired second metal interconnections; removing completely all said photoresist layers; depositing a passivating layer conformally on the surface of said exposed first and second metal interconnections thereby completing said air-insulated metal interconnections.
Claim 2
Independent Claim
391 words
A method for fabricating air-insulated metal interconnections on a substrate comprising the steps of: providing a substrate having device areas surrounded and electrically insulated from each other by field oxide regions, said device areas having partially completed devices formed from a patterned first polysilicon layer; depositing a first insulating layer on said partially completed devices on said substrate; planarizing said first insulating layer; depositing a second insulating layer on said first insulating layer; forming contact holes in said first and second insulating layers to said patterned first polysilicon layer and to said device areas on said substrate; filling selectively said contact holes with a first conducting layer and thereby forming metal plugs; depositing a first negative photoresist layer on said second insulating layer and on said metal plugs; patterning said first negative photoresist layer and forming open regions extending over said metal plugs; depositing a conformal second conducting layer on said first negative photoresist layer and in said open regions electrically contacting said metal plugs; depositing a third conducting layer over said second conducting layer sufficiently thick to fill said open regions in said first negative photoresist layer; planarizing said third conducting layer leaving portions of said third conducting layer in said openings while removing said third conducting layer over and to said first negative photoresist layer thereby forming planar first metal interconnections; depositing a positive photoresist layer over said metal interconnections; depositing a second negative photoresist layer on said positive photoresist layer; patterning said second negative photoresist layer leaving open regions over areas of said positive photoresist where second metal interconnections are desired; exposing and developing in said positive photoresist layer and forming via holes to said first metal interconnections; depositing a conformal fourth conducting layer on said second negative photoresist layer and in said open regions in said second negative photoresist layer; depositing a fifth conducting layer over said fourth conducting layer sufficiently thick to fill said open regions in said second negative photoresist layer; planarizing said fifth conducting layer leaving portions of said fifth conducting layer in said openings while removing said fourth conducting layer over and to said second negative photoresist layer thereby forming said desired second metal interconnections; removing completely all said photoresist layers; depositing a passivating layer conformally on the surface of said exposed first and second metal interconnections thereby completing said air-insulated metal interconnections.
Claim 3
Dependent Claim
27 words
The method of claim 1, wherein said patterned first polysilicon layer is heavily N + doped and has a thickness of between about 2000 and 5000 Angstroms.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said first insulating layer is a borophosphosilicate glass (BPSG) planarized by chemical/mechanical polishing.
Claim 5
Dependent Claim
25 words
The method of claim 3, wherein said first insulating layer has a thickness of between about 5000 and 15000 Angstroms after said chemical/ mechanical polishing.
Claim 6
Dependent Claim
23 words
The method of claim 1, wherein said second insulating layer is silicon nitride having a thickness of between about 500 and 2000 Angstroms.
Claim 7
Dependent Claim
14 words
The method of claim 1, wherein said metal plugs are titanium nitride and tungsten.
Claim 8
Dependent Claim
18 words
The method of claim 1, wherein said first negative photoresist layer is between about 8000 and 10000 Angstroms.
Claim 9
Dependent Claim
49 words
The method of claim 1, wherein said second and fourth conducting layers are deposited at room temperature and are composed of a titanium layer having a thickness of between about 200 and 1000 Angstroms, and a titanium nitride layer having a thickness of between about 200 and 1000 Angstroms.
Claim 10
Dependent Claim
27 words
The method of claim 1, where said third conducting layer is copper deposited by electroless plating and has a thickness of between about 8000 and 12000 Angstroms.
Claim 11
Dependent Claim
15 words
The method of claim 1, wherein said third conducting layer is planarized by chemical/mechanical polishing.
Claim 12
Dependent Claim
20 words
The method of claim 1, wherein said positive photoresist layer has a thickness of between about 6000 and 8000 Angstroms.
Claim 13
Dependent Claim
19 words
The method of claim 1, wherein said second negative photoresist layer is between about 10000 and 12000 Angstroms thick.
Claim 14
Dependent Claim
26 words
The method of claim 1, wherein said fifth conducting layer is copper deposited by electroless plating to a thickness of between about 12000 and 15000 Angstroms.
Claim 15
Dependent Claim
18 words
The method of claim 1, wherein said photoresist layers are removed by plasma ashing in an oxygen ambient.
Claim 16
Dependent Claim
29 words
The method of claim 1, wherein said passivating layer is composed of aluminum oxide (Al 2 O 3 ) having a thickness of between about 200 and 500 Angstroms.
Claim 17
Independent Claim
435 words
A method for fabricating multilevel air-insulated metal interconnections on a substrate for integrated circuits comprising the steps of: (a) providing a substrate having device areas surrounded and electrically insulated from each other by field oxide regions, said device areas having partially completed devices formed from a patterned first polysilicon layer; (b) depositing a first insulating layer on said partially completed devices on said substrate; (c) planarizing said first insulating layer; (d) depositing a second insulating layer on said first insulating layer; (e) forming contact holes in said first and second insulating layers to said patterned first polysilicon layer and to said device areas on said substrate; (f) filling selectively said contact holes with a first conducting layer and thereby forming metal plugs; (g) depositing a first negative photoresist layer on said second insulating layer and on said metal plugs; (h) patterning said first negative photoresist layer and forming open regions extending over said metal plugs; (i) depositing a conformal second conducting layer on said first negative photoresist layer and in said open regions electrically contacting said metal plugs; (j) depositing a third conducting layer over said second conducting layer sufficiently thick to fill said open regions in said first negative photoresist layer; (k) planarizing said third conducting layer leaving portions of said third conducting layer in said openings while removing said third conducting layer over and to said first negative photoresist layer thereby forming planar first metal interconnections; (l) depositing a positive photoresist layer over said metal interconnections; (m) depositing a second negative photoresist layer on said positive photoresist layer; (n) patterning said second negative photoresist layer leaving open regions over areas of said positive photoresist where second metal interconnections are desired; (o) exposing and developing in said positive photoresist layer and forming via holes to said first metal interconnections; (p) depositing a conformal fourth conducting layer on said second negative photoresist layer and in said open regions in said second negative photoresist layer; (q) depositing a fifth conducting layer over said fourth conducting layer sufficiently thick to fill said open regions in said second negative photoresist layer; (r) planarizing said fifth conducting layer leaving portions of said fifth conducting layer in said openings while removing said fourth conducting layer over and to said second negative photoresist layer thereby forming said desired second metal interconnections; (s) removing completely all said photoresist layers; (t) depositing a passivating layer conformally on the surface of said exposed first and second metal interconnections thereby completing said air-insulated metal interconnections. (u) repeating steps (l) through (t) for each additional level of metal interconnections required to wire up said integrated circuits.
Claim 18
Independent Claim
435 words
A method for fabricating multilevel air-insulated metal interconnections on a substrate for integrated circuits comprising the steps of: (a) providing a substrate having device areas surrounded and electrically insulated from each other by field oxide regions, said device areas having partially completed devices formed from a patterned first polysilicon layer; (b) depositing a first insulating layer on said partially completed devices on said substrate; (c) planarizing said first insulating layer; (d) depositing a second insulating layer on said first insulating layer; (e) forming contact holes in said first and second insulating layers to said patterned first polysilicon layer and to said device areas on said substrate; (f) filling selectively said contact holes with a first conducting layer and thereby forming metal plugs; (g) depositing a first negative photoresist layer on said second insulating layer and on said metal plugs; (h) patterning said first negative photoresist layer and forming open regions extending over said metal plugs; (i) depositing a conformal second conducting layer on said first negative photoresist layer and in said open regions electrically contacting said metal plugs; (j) depositing a third conducting layer over said second conducting layer sufficiently thick to fill said open regions in said first negative photoresist layer; (k) planarizing said third conducting layer leaving portions of said third conducting layer in said openings while removing said third conducting layer over and to said first negative photoresist layer thereby forming planar first metal interconnections; (l) depositing a positive photoresist layer over said metal interconnections; (m) depositing a second negative photoresist layer on said positive photoresist layer; (n) patterning said second negative photoresist layer leaving open regions over areas of said positive photoresist where second metal interconnections are desired; (o) exposing and developing in said positive photoresist layer and forming via holes to said first metal interconnections; (p) depositing a conformal fourth conducting layer on said second negative photoresist layer and in said open regions in said second negative photoresist layer; (q) depositing a fifth conducting layer over said fourth conducting layer sufficiently thick to fill said open regions in said second negative photoresist layer; (r) planarizing said fifth conducting layer leaving portions of said fifth conducting layer in said openings while removing said fourth conducting layer over and to said second negative photoresist layer thereby forming said desired second metal interconnections; (s) removing completely all said photoresist layers; (t) depositing a passivating layer conformally on the surface of said exposed first and second metal interconnections thereby completing said air-insulated metal interconnections. (u) repeating steps (l) through (t) for each additional level of metal interconnections required to wire up said integrated circuits.
Claim 19
Dependent Claim
27 words
The method of claim 16, wherein said patterned first polysilicon layer is heavily N + doped and has a thickness of between about 2000 and 5000 Angstroms.
Claim 20
Dependent Claim
19 words
The method of claim 16, wherein said first insulating layer is a borophosphosilicate glass (BPSG) planarized by chemical/mechanical polishing.
Claim 21
Dependent Claim
24 words
The method of claim 18, wherein said first insulating layer has a thickness of between about 5000 and 15000 Angstroms after said chemical/mechanical polishing.
Claim 22
Dependent Claim
23 words
The method of claim 16, wherein said second insulating layer is silicon nitride having a thickness of between about 500 and 2000 Angstroms.
Claim 23
Dependent Claim
14 words
The method of claim 16, wherein said metal plugs are titanium nitride and tungsten.
Claim 24
Dependent Claim
18 words
The method of claim 16, wherein said first negative photoresist layer is between about 8000 and 10000 Angstroms.
Claim 25
Dependent Claim
49 words
The method of claim 16, wherein said second and fourth conducting layers are deposited at room temperature and are composed of a titanium layer having a thickness of between about 200 and 1000 Angstroms, and a titanium nitride layer having a thickness of between about 200 and 1000 Angstroms.
Claim 26
Dependent Claim
27 words
The method of claim 16, where said third conducting layer is copper deposited by electroless plating and has a thickness of between about 8000 and 12000 Angstroms.
Claim 27
Dependent Claim
15 words
The method of claim 16, wherein said third conducting layer is planarized by chemical/mechanical polishing.
Claim 28
Dependent Claim
20 words
The method of claim 16, wherein said positive photoresist layer has a thickness of between about 6000 and 8000 Angstroms.
Claim 29
Dependent Claim
19 words
The method of claim 16, wherein said second negative photoresist layer is between about 10000 and 12000 Angstroms thick.
Claim 30
Dependent Claim
26 words
The method of claim 16, wherein said fifth conducting layer is copper deposited by electroless plating to a thickness of between about 12000 and 15000 Angstroms.
Claim 31
Dependent Claim
18 words
The method of claim 16, wherein said photoresist layers are removed by plasma ashing in an oxygen ambient.
Claim 32
Dependent Claim
29 words
The method of claim 16, wherein said passivating layer is composed of aluminum oxide (Al 2 O 3 ) having a thickness of between about 200 and 500 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |