Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby

Claim 1

A method of forming a device on a surface of a conductive substrate comprising: forming a dielectric layer over said surface, said dielectric layer having a top level; forming a trench with sidewalls through said dielectric layer to expose a portion of said surface; forming a barrier layer narrowing said trench and covering said surface and covering said top level and said sidewalls of said dielectric layer; depositing copper as a blanket overfilling said narrow hole and covering said top level; subtracting material from the surface of said copper leaving a thin layer of said copper covering said barrier layer and said dielectric layer, forming a copper passivation combination with an element selected from silicon and germanium thereby lowering remaining portions of said copper below said dielectric top level in said narrow hole; and planarizing said copper passivation combination to said top level leaving a thin layer of said compound covering said copper conductor in said narrow hole.

Claim 2

A method of forming a device on a surface of a conductive substrate comprising: forming a dielectric layer over said surface, said dielectric layer having a top level; forming a trench with sidewalls through said dielectric layer to expose a portion of said surface; forming a barrier layer narrowing said trench and covering said surface and covering said top level and said sidewalls of said dielectric layer; depositing copper as a blanket overfilling said narrow hole and covering said top level; subtracting material from the surface of said copper leaving a thin layer of said copper covering said barrier layer and said dielectric layer, forming a copper passivation combination with an element selected from silicon and germanium thereby lowering remaining portions of said copper below said dielectric top level in said narrow hole; and planarizing said copper passivation combination to said top level leaving a thin layer of said compound covering said copper conductor in said narrow hole.

Claim 15

A method of forming a copper conductor in a thin film electronic device over a conductive substrate with a top surface comprising: forming a dielectric layer superjacent to said top surface of said conductive substrate, said dielectric layer having a top surface located at a dielectric top level, patterning said dielectric layer to etch a hole therethrough with a dry plasma to etch a trench down to said conductive substrate exposing a portion of said top surface of said conductive substrate and forming exposed sidewalls of said dielectric layer, forming a barrier layer composed of a material selected from the group consisting of tantalum and tantalum nitride, said barrier layer being superjacent to, as follows: a) said top surface of said conductive substrate, b) said dielectric layer including said exposed top surface of said conductive substrate and said exposed sidewalls of said dielectric layer, said barrier layer forming a narrower hole in said trench, forming a copper conductor having a surface, said copper conductor being superjacent to said barrier layer, said copper conductor overfilling said narrower hole, removing material from said surface of said copper conductor by a CMP etching process leaving a lowered copper surface with a thin layer of copper over said barrier layer above said top surface of said dielectric layer, adding silicon or germanium to said copper forming an interface between said copper and said copper/silicon compound or copper/germanium compound located below said dielectric top level in said narrower hole in said trench, and then subtracting material from the surface of said copper compound by a CMP etching process to planarize said copper compound down to said dielectric top level leaving a thin layer of said compound covering said copper conductor in said narrower hole.

Claim 16

A method of forming a copper conductor in a thin film electronic device over a conductive substrate with a top surface comprising: forming a dielectric layer superjacent to said top surface of said conductive substrate, said dielectric layer having a top surface located at a dielectric top level, patterning said dielectric layer to etch a hole therethrough with a dry plasma to etch a trench down to said conductive substrate exposing a portion of said top surface of said conductive substrate and forming exposed sidewalls of said dielectric layer, forming a barrier layer composed of a material selected from the group consisting of tantalum and tantalum nitride, said barrier layer being superjacent to, as follows: a) said top surface of said conductive substrate, b) said dielectric layer including said exposed top surface of said conductive substrate and said exposed sidewalls of said dielectric layer, said barrier layer forming a narrower hole in said trench, forming a copper conductor having a surface, said copper conductor being superjacent to said barrier layer, said copper conductor overfilling said narrower hole, removing material from said surface of said copper conductor by a CMP etching process leaving a lowered copper surface with a thin layer of copper over said barrier layer above said top surface of said dielectric layer, adding silicon or germanium to said copper forming an interface between said copper and said copper/silicon compound or copper/germanium compound located below said dielectric top level in said narrower hole in said trench, and then subtracting material from the surface of said copper compound by a CMP etching process to planarize said copper compound down to said dielectric top level leaving a thin layer of said compound covering said copper conductor in said narrower hole.