Frequency-doubling delay locked loop

Claim 2

A delay locked loop for generating an output clock signal in response to a reference input clock signal comprising: a) a delay line having a predetermined number of serially coupled delay stages, each of said delay stages providing a delay stage tap output; b) a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of said combining cells providing first and second complementary outputs, said outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal; c) a selector responsive to a selection control signal for selecting an output from one of a pair of complementary outputs of one of said combining cells, to produce said output clock signal; d) a phase detector responsive to said output clock signal and said reference input clock signal to control said selector for selecting an optimum complimentary output for synchronizing said reference input clock signal and said output clock signal.

Claim 3

A delay locked loop as described in claim 1 , including N serially coupled delay stages providing N tap outputs to N/4 combining circuit cells and said N/4 combining cells provide N/2 evenly spaced phases of the output clock signal whose frequency is twice that of the reference input clock.

Claim 4

A delay locked loop as described in claim 1 , wherein each of said combining circuit cells are responsive to a rising edge of a pulse of said input clock for initiating a rising pulse of said output clock and responsive to a delayed version of said input pulse for clearing said pulse and responsive to a falling edge of said input clock pulse to initiate a rising edge of a second output pulse and responsive to a delayed version of said input falling edge for clearing said second output pulse.

Claim 5

A delay locked loop as described in claim 1 , wherein said optimum complementary output is an output whose phase is a closest match to said input reference clock signal's phase.

Claim 6

A frequency multiplier circuit for generating an output clock signal in response to a rising edge of a reference input clock signal, said multiplier comprising: a delay line for receiving and delaying said reference input clock signal, said delay line having a plurality of serially coupled delay stages each having a delay stage tap output; a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal; a selector coupled to said combining cell outputs for selecting an output from said combining cells outputs for producing said output clock signal; wherein said frequency multiplier circuit is a delay locked loop; wherein the number of said plurality of combining cells is divisible by 4; wherein each of said delay stage outputs coupled to said combining cell inputs is separated by at least 90 degrees; and, wherein said combining cells comprising a flip-flop circuit for producing said combining cell output.

Claim 7

A frequency multiplier circuit for generating an output clock signal in response to a rising edge of a reference input clock signal, said multiplier comprising: a delay line for receiving and delaying said reference input clock signal, said delay line having a plurality of serially coupled delay stages each having a delay stage tap output; a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal; a selector coupled to said combining cell outputs for selecting an output from said combining cells outputs for producing said output clock signal; wherein said frequency multiplier circuit is a delay locked loop; wherein the number of said plurality of combining cells is divisible by 4; wherein each of said delay stage outputs coupled to said combining cell inputs is separated by at least 90 degrees; and, wherein said combining cells comprising a flip-flop circuit for producing said combining cell output.

Claim 8

A frequency multiplier circuit as described in claim 5 , wherein said plurality of combining cells further comprise: a) a first pair of edge detectors comprising a rising edge detector and a falling edge detector coupled to selective ones of said delay stage outputs for providing a first and second set signals; b) a second pair of said rising and falling edge detectors coupled to selective ones of said delay stage outputs for providing a first and second reset signals; c) a first OR gate for combining said first and second set signals, producing a common set signal; d) a second OR gate for combining said first and second reset signals, producing a common reset signal; and e) a flip-flop circuit for receiving said common set and reset signals and for providing a signal having a multiplied frequency of said input clock signal.

Claim 9

A frequency multiplier circuit as described in claim 5 , further comprising a phase detector for receiving said output clock signal and said reference input clock signal for controlling said selector for synchronizing said reference input clock signal and said output clock signal.