EP0570158A2
Expired / Lapsed
EP
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A stable clock generator circuit with clock multiplication
Assignee: National Semiconductor Corp
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Filing: 1993-05-07
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Granted: —
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Expires: 2013-05-07
Abstract
Abstract An integrated circuit, such as a microprocessor or math co-processor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input clock signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Further, the duty cycle of the generated clock is independent of the input clock signal. The circuitry for generating a plurality of clock edges includes one or more programmable delay stages. Each delay stage comprises fixed and variable portions; the fixed portion preferably includes a series of logic elements of various types selected to match the worst case clock phase delay and to match circuit speed variations, and the variable portion of the delay stage selects as propagation delay by way of programmable elements.
Inventors
- 👤 John K. Eitrheim
- 👤 Richards B. Reis
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 12:01
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K5/00; H03K5/00006; H03K5/15; H03K5/15013; H03K5/15026
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
57 words
Circuitry for generating a clock signal responsive to an input clock signal, comprising: circuitry for detecting an active edge of said input clock signal; circuitry for generating a plurality of clock edges responsive to said detection of said active edge; and circuitry for inhibiting said edge generating circuitry after generation of a predetermined number of clock edges.
Claim 2
Dependent Claim
24 words
The clock generating circuitry of Claim 1 wherein said inhibiting circuitry is reset responsive to detection of an active edge of the input clock.
Claim 3
Dependent Claim
73 words
The clock generating circuitry of Claim 1 or Claim 2 wherein said edge generating circuitry comprises: delay circuitry for receiving a signal and outputting said same signal after a predefined delay; edge detection circuitry coupled to said delay circuitry for detecting a predetermined transition of the output of said delay circuitry and generating a detection signal in response thereto; and transition circuitry for generating a clock transition responsive to said edge detection circuitry.
Claim 4
Dependent Claim
54 words
The clock generating circuitry of Claim 3 wherein said delay circuitry comprises first and second delay stages, the first delay stage defining the duration of the high logic level phase of the generated clock signal and the second delay stage defining the duration of the low logic level phase of the generated clock signal.
Claim 5
Dependent Claim
54 words
The clock generating circuitry of any one of the preceding claims wherein said inhibiting circuitry comprises: counting circuitry for counting clock edges; and comparator circuitry for comparing the output of said counting circuitry with a predetermined number and for generating a signal indicating whether the output of said counting circuitry equals said predetermined number.
Claim 6
Independent Claim
55 words
A method of generating a clock signal responsive to an input clock signal, comprising the steps of: detecting an active edge of said input clock signal; generating a plurality of clock edges responsive to said detection of said active edge; and inhibiting said edge generating circuitry after generation of a predetermined number of clock edges.
Claim 7
Dependent Claim
51 words
The method of Claim 6 wherein said generating step comprises the step of: receiving a signal and outputting said same signal after a predefined delay; detecting a predetermined transition of the delayed signal and generating a detection signal in response thereto; and generating a clock transition responsive to said detection signal.
Claim 8
Dependent Claim
49 words
The method of Claim 6 or Claim 7 wherein said inhibiting step comprises the steps of: counting clock edges of the clock signal; comparing the number of counted edges with a predetermined number and generating a signal indicating whether the output of said counting circuitry equals said predetermined number.
Claim 9
Dependent Claim
147 words
An integrated circuit, comprising: first and second functional modules, each having an associated clock input; and a clock control circuit for generating first and second output clock signals to said first and second functional modules, respectively, responsive to an input clock signal received at a clock input and to an enable signal received at an enable input, said clock generator circuit comprising: a first clock generator circuit, coupled to receive said input clock signal, for generating said first output clock signal responsive to said input clock signal, said first output clock signal being at a first frequency; and a second clock generator circuit, coupled to receive an enable signal and said input clock signal, for generating said second output clock signal responsive to said input clock signal, said second output clock signal being at a second frequency responsive to said enable signal being at a first state.
Claim 10
Dependent Claim
83 words
The integrated circuit of claim 9, further comprising: an enable bond pad, coupled to said clock control circuit, for communicating said enable signal thereto; first and second bias supply terminals, for receiving first and second bias voltages, respectively; and wherein said enable bond pad presents said first state to said clock control circuit responsive to being connected to said first bias supply terminal, and presents said second state to said clock control circuit responsive to being connected to said second bias supply terminal.
Claim 11
Dependent Claim
127 words
The integrated circuit of claim 9 or Claim 10 further comprising: a mode select input for indicating first and second clock modes; and wherein said second clock generator circuit further comprises: a frequency divider, coupled to said clock input of said clock control circuit, for generating a divided frequency output clock signal to the clock input of said first functional module responsive to said input clock signal; and a select circuit, responsive to said mode select input, for enabling the set and reset circuits and disabling the frequency divider responsive to said mode select input indicating said first clock mode, and for selecting the divided frequency output clock signal and disabling the set and reset circuits responsive to said mode select input indicating said second clock mode.
Claim 12
Dependent Claim
48 words
The integrated circuit of claim 11, wherein said mode select input comprises a bond pad; wherein said first clock mode is selected by connecting said bond pad to a first voltage; and wherein said second clock mode is selected by connecting said bond pad to a second voltage.
Claim 13
Dependent Claim
81 words
A clock generator circuit for generating, at its output, a first output clock signal responsive to an input clock signal received at its input, comprising: a first delay stage connected to receive and delay the input clock signal; a set circuit connected to set a latch responsive to a first transition of said input clock signal; and a reset circuit connected to reset the latch responsive to a first transition of the delayed input clock signal from the first delay stage.
Claim 14
Dependent Claim
105 words
The clock generator circuit of claim 13, further comprising: a second delay stage connecting the output of the first delay stage to the set circuit; a third delay stage connecting the output of the second delay stage to the reset circuit; said set circuit detecting the first transition of said clock input and the first transition at said second delay stage, and for setting said latch responsive to said detection by said set circuit; and said reset circuit detecting the first transition at the output of the output of said third delay stage, and resetting said latch responsive to said detection by said reset circuit.
Claim 15
Dependent Claim
27 words
The clock generator circuit of claim 13 or Claim 14 wherein said delay stage comprises a plurality of logic elements, each corresponding to a different logic function.
Claim 16
Dependent Claim
64 words
The clock generator circuit of claim 13 Claim 14 or Claim 15 wherein said first delay stage comprises: a fixed delay stage; and a variable delay stage, connected in series with said fixed delay stage, and comprising: a plurality of delay elements; and a select circuit for selecting among said plurality of delay elements to set the propagation delay of said variable delay stage.
Claim 17
Dependent Claim
61 words
The clock generator circuit of claim 16, wherein said variable delay stage further comprises: a plurality of programmable elements, coupled to the select circuit of said variable delay stage and associated with each of said plurality of delay elements, each programmable element indicating whether or not its associated delay element is to be connected in series in said variable delay stage.
Claim 18
Dependent Claim
90 words
The clock generator circuit of any one of Claims 13 to 17, further comprising: a plurality of multiplexers, each having a first input coupled to an associated programmable element, each having a second input coupled to an associated select line, and each having a control input coupled to a test mode input to select, responsive to said test mode input, either its associated select line or its associated programmable element for determining whether or not its associated delay element is to be connected in series in said variable delay stage.
Claim 19
Independent Claim
95 words
A method for generating an internal clock signal in an integrated circuit responsive to an input clock signal, comprising the steps of: setting a latch to a first state responsive to a first transition of said input clock signal; applying said input clock signal to a first delay stage to generate a first delayed input clock signal; resetting said latch responsive to a first transition of said first delayed input clock signal; and wherein said resetting step is performed responsive to either a low-to-high or a high-to-low transition of said first delayed input clock signal.
Claim 20
Dependent Claim
14 words
The method of claim 19, further comprising: selecting the duration of said delaying step.
Claim 21
Dependent Claim
89 words
The method of claim 19 or claim 20, further comprising: applying said first delayed input clock signal to a second delay stage to generate a second delayed input clock signal; setting said latch to the first state responsive to a first transition of said second delayed input clock signal; applying said second delayed input clock signal to a third delay stage to generate a third delayed input clock signal; and resetting said latch to the second state responsive to a first transition of said third delayed input clock signal.
References Cited (Backward Citations)
No citation records indexed.
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