Voltage controlled oscillator and phase-locked loop circuit

Claim 2

A voltage-controlled oscillator, comprising: a voltage controlled variable delay unit D(N) which comprises first amplifier elements AP1(1), AP1(2), . . . , AP1(N) of number N in which a pair of input signal lines and a pair of output signal lines are connected with each other, wherein said voltage-controlled delay unit can control a delay time for transmitting a signal from a pair of reference input signal lines to a pair of reference output signal lines; and ring oscillators P(N) of number Q of one or more which comprises second amplifier elements AM(1), AM(2), . . . , AM(M) of number M in which phase correctors M(1), M(2), . . . , M(M) of number M are connected to the respective pair of output signal lines from first amplifier elements AP2(1), AP2(2), . . . , AP2(M) of number M, wherein an end pair of input signal lines and an end pair of output signal lines are connected with each other in the form of ring; wherein said pair of output signal lines of each of said first amplifier elements AP1(1), AP1(2), . . . , AP1(N) is connected to a first pair of input terminals and second pair of input terminals of each of said phase correctors M(1), M(2), . . . , M(M) included in said ring oscillator P(N), followed by procedures that, between said ring oscillators, P(N/2), P(N/4), . . . , P(N/(2×Q)), of number Q, a pair of output signal lines of each of said phase correctors M(1), M(2) . . . , M(N/(2×X)) included in a ring oscillator P(N/(2×X)) is connected to a first pair of input terminals and second pair of input terminals of each of said phase correctors M(1), M(2), . . . , M(N/(4×X)) included in a ring oscillator P(N/(4×X)), wherein X is in the range of 1 to Q-1.

Claim 3

A voltage-controlled oscillator, according to claim 1, wherein: each of said first amplifier elements is provided with a pair of input signal lines, a pair of output signal lines and one or more control signal line and can function as differential amplifier and control a delay time on which a differential signal is transmitted from said pair of input signal lines to said pair of output signal lines by a control signal through said control signal line.

Claim 4

A voltage-controlled oscillator, according to claim 1, wherein: each of said phase correctors is provided with a pair of input signal lines, a pair of output signal lines, a first pair of input terminals, a second pair of input terminals, a switching element which is shut or opened such that said pair of input signal lines and pair of output signal lines have a given logical level when said first pair of input terminals and second pair of input terminals have a different logical level each other, and which is shut or opened such that said pair of input signal lines and pair of output signal lines have a logical level reversed to said given logical level when said first pair of input terminals and second pair of input terminals have the same logical level.

Claim 5

A voltage-controlled oscillator, according to claim 3, wherein: said switching element comprises a MOS transistor or bipolar transistor.

Claim 6

A phase-locked loop circuit, comprising: a phase comparator which inputs a first and second input signals and outputs a third control signal corresponding to a phase difference through one or more signal lines; a charge pump circuit which inputs said third control signal and outputs a fourth control signal; a low-pass filter circuit which inputs said fourth control signal and outputs a signal obtained by attenuating a high-frequency component of said fourth control signal; and a voltage-controlled oscillator which inputs said output signal from said low-pass filter circuit as a control signal; said voltage-controlled oscillator comprising a voltage-controlled variable delay unit D(N) which comprises first amplifier elements AP1(1), AP1(2), . . . , AP1(N) of number N in which a pair of input signal lines and a pair of output signal lines are connected with each other, wherein said voltage-controlled delay unit can control a delay time for transmitting a signal from a pair of reference input signal lines to a pair of reference output signal lines; and ring oscillators P(N) of number Q of one or more which comprises second amplifier elements AM(1), AM(2), . . . , AM(M) of number M in which phase correctors M(1), M(2), . . . , M(M) of number M are connected to the respective pair of output signal lines from first amplifier elements AP2(1), AP2(2), . . . , AP2(M) of number M, wherein an end pair of input signal lines and an end pair of output signal lines are connected with each other in the form of a ring; wherein said pair of output signal lines of each of said first amplifier elements AP1(1), AP1(2), . . . , AP1(N) is connected to a first pair of input terminals and second pair of input terminals of each of said phase correctors M(1), M(2), . . . , M(M) included in said ring oscillator P(N), followed by procedures that, between said ring oscillators, P(N/2), P(N/4), . . . , P(N/(2×Q)), of number Q, a pair of output signal lines of each of said phase correctors M(1), M(2) . . . , M(N/(2×X)) included in a ring oscillator P(N/(2×X)) is connected to a first pair of input terminals and second pair of input terminals of each of said phase correctors M(1), M(2), . . . , M(N/(4×X)) included in a ring oscillator P(N/(4×X)), wherein X is in the range of 1 to Q-1, and wherein a reference clock from outside is given to said voltage-controlled oscillator through a pair of reference input signal lines and is given to said phase comparator as said first input signal, and said second input signal is given to said phase comparator through a pair of reference output signal lines from said voltage-controlled oscillator.

Claim 7

A phase-locked loop circuit, comprising: a phase comparator which inputs a first and second input signals and outputs a third control signal corresponding to a phase difference through one or more signal lines; a charge pump circuit which inputs said third control signal and outputs a fourth control signal; a low-pass filter circuit which inputs said fourth control signal and outputs a signal obtained by attenuating a high-frequency component of said fourth control signal; and a voltage-controlled oscillator which inputs said output signal from said low-pass filter circuit as a control signal; said voltage-controlled oscillator comprising a voltage-controlled variable delay unit D(N) which comprises first amplifier elements AP1(1), AP1(2), . . . , AP1(N) of number N in which a pair of input signal lines and a pair of output signal lines are connected with each other, wherein said voltage-controlled delay unit can control a delay time for transmitting a signal from a pair of reference input signal lines to a pair of reference output signal lines; and ring oscillators P(N) of number Q of one or more which comprises second amplifier elements AM(1), AM(2), . . . , AM(M) of number M in which phase correctors M(1), M(2), . . . , M(M) of number M are connected to the respective pair of output signal lines from first amplifier elements AP2(1), AP2(2), . . . , AP2(M) of number M, wherein an end pair of input signal lines and an end pair of output signal lines are connected with each other in the form of a ring; wherein said pair of output signal lines of each of said first amplifier elements AP1(1), AP1(2), . . . , AP1(N) is connected to a first pair of input terminals and second pair of input terminals of each of said phase correctors M(1), M(2), . . . , M(M) included in said ring oscillator P(N), followed by procedures that, between said ring oscillators, P(N/2), P(N/4), . . . , P(N/(2×Q)), of number Q, a pair of output signal lines of each of said phase correctors M(1), M(2) . . . , M(N/(2×X)) included in a ring oscillator P(N/(2×X)) is connected to a first pair of input terminals and second pair of input terminals of each of said phase correctors M(1), M(2), . . . , M(N/(4×X)) included in a ring oscillator P(N/(4×X)), wherein X is in the range of 1 to Q-1, and wherein a reference clock from outside is given to said voltage-controlled oscillator through a pair of reference input signal lines and is given to said phase comparator as said first input signal, and said second input signal is given to said phase comparator through a pair of reference output signal lines from said voltage-controlled oscillator.

Claim 8

A phase-locked loop circuit, according to claim 5, wherein: each of said first amplifier elements is provided with a pair of input signal lines, a pair of output signal lines and one or more control signal line and can function as differential amplifier and control a delay time on which a differential signal is transmitted from said pair of input signal lines to said pair of output signal lines by a control signal through said control signal line.

Claim 9

A phase-locked loop circuit, according to claim 5, wherein: each of said phase correctors is provided with a pair of input signal lines, a pair of output signal lines, a first pair of input terminals, a second pair of input terminals, a switching element which is shut or opened such that said pair of input signal lines and pair of output signal lines have a given logical level when said first pair of input terminals and second pair of input terminals have a different logical level each other, and which is shut or opened such that said pair of input signal lines and pair of output signal lines have a logical level reversed to said given logical level when said first pair of input terminals and second pair of input terminals have the same logical level.

Claim 10

A phase-locked loop circuit, according to claim 7, wherein: said switching element comprises a MOS transistor or bipolar transistor.